Jtag interface, Ee jtag interface – Echelon Series 6000 Chip databook User Manual
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failure in the device. The write-protected part of the flash contains the bootloader, active
system image, and active application.
JTAG Interface
All Series 6000 chips provide an interface for the Institute of Electrical and Electronics
Engineers (IEEE) Standard Test Access Port and Boundary-Scan Architecture (IEEE 1149.1-
1990) of the Joint Test Action Group (JTAG) to allow a Series 6000 chip to be included in the
boundary-scan chain for device production tests.
You can obtain a Boundary Scan Description Language (BSDL) file from the Echelon Web
site:
•
for a Neuron 6000 Processor
•
http://www.echelon.com/products/components/ic/ft5000/default.htm for an FT 6000
Smart Transceiver
The JTAG interface for Series 6000 chips can operate at up to 5 MHz. The JTAG interface
includes the following pins:
•
TDI — Test Data In (pin 21)
Used to shift in serial test instructions and data. Connect this pin to the TDI signal
of a JTAG connector or to the TDO signal of an upstream device in a JTAG chain.
•
TDO — Test Data Out (pin 22)
Used to shift out serial test instructions and data. When TDO is not being driven by
the internal circuitry, the pin is in a high impedance state. Connect this pin to the
TDO signal of a JTAG connector or to the TDI signal of a downstream device in a
JTAG chain.
•
TCK — Test Clock (pin 19)
Provides the clock to run the test access port (TAP) controller state machine, which
controls the JTAG data and instruction registers. You can stop the TCK signal in
either the high or low state, and you can set the clock frequency up to 5 MHz. The
TCK pin supports hysteresis; the typical hysteresis is approximately 300 mV.
•
TMS — Test Mode Select (pin 20)
Controls test operations of the TAP controller. On the falling edge of the TCK signal,
depending on the state of the TMS signal, the TAP controller state machine changes
state.
•
TRST~ — Test Reset (pin 17)
Resets the TAP controller state machine.
These pins comply with the JTAG standard protocol (IEEE 1149.1) for boundary scan
operations, and can be used with industry-standard JTAG tools. Each of these pins also
includes an internal pull-up resistor, as recommended by the JTAG standard. These pull-
ups are only strong enough to pull the input up when the pin is floating, but not strong
enough for an external load.
The JTAG interface for Series 6000 chips supports the following JTAG instructions (see the
device BSDL file for instruction register codes):
•
BYPASS — bypasses the current device (to allow connection to another device in the
chain)
Required by the IEEE 1149.1 standard
Series 6000 Chip Data Book
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