Echelon Series 6000 Chip databook - Manual (Page 112)

Overview
Echelon’s Neuron Chips and Smart Transceivers connect to application-specific external
hardware through 11 or 12 I/O pins, named IO0-IO11. You can configure these pins to
provide flexible input and output (I/O) functions with minimal external circuitry. These
functions are described as I/O models.
The Neuron C programming language allows the application programmer to declare I/O
objects that use one or more I/O pins. An I/O object is a software instance of an I/O model,
and provides programmable access to an I/O driver for a specified on-chip I/O hardware
configuration and a specified input or output waveform definition. Programs can then refer
to most of these objects through io_in() and io_out() system calls to perform the actual
input or output function during execution of the program. Because events are associated
with changes in input values, the task scheduler can execute associated application code
when these changes occur.
There are many different I/O models available for use with the Neuron Chips and Smart
Transceivers. Most I/O models are available in system images by default. If an I/O model is
required by an application, but is not included in the default system image, the development
tool links the appropriate models into available memory space. For Series 6000 device
designs, the model is added to the application image.
Series 6000 chips also support application-specific interrupts, which can trigger on either or
both edges, or on either level, for any of the I/O pins, regardless of any associated I/O object.
See the Neuron C Programmer’s Guide for more information about interrupts.
See the I/O Model Reference for Smart Transceivers and Neuron Chips for more information
about the available I/O models and how to use them.
Two 16-Bit Timer/Counters
Two classes of I/O model use internal timer/counters. The timer/counters are implemented
as a register that is writable by the application processor, a 16-bit counter, and a latch that is
readable by the processor. The 16-bit registers are accessed 1 byte at a time. Series 6000
chips have two timer/counters, as shown in Figure 43:
• Timer/Counter 1, with input that is selectable among pins IO4 – IO7 and output to
pin IO0
• Timer/Counter 2, with input from pin IO4 and output to pin IO1
100 Input/Output Interfaces for the Series 6000