Echelon Series 6000 Chip databook - Manual (Page 36)

On-Chip Memory
A Series 6000 chip has the following on-chip memory:
• 16 KB of read-only memory (ROM)
The ROM holds an initial system image that is used only to bootstrap the system
from flash or to initially load the flash over the network during manufacturing of a
Series 6000 device. Please see Device Programming for further details.
• 64 KB of random access memory (RAM)
The RAM provides memory for user applications and data, stack segments for each
processor, and network and application buffers. The RAM is partitioned according to
a logical memory map, as described in Memory Map.
A Series 6000 chip contains no internal writable non-volatile memory (such as EEPROM
memory) for application use. However, each Series 6000 chip does contain a unique IEEE
MAC ID in non-volatile read-only memory.
The chip’s memory management block allows the RAM to emulate both ROM and NVM by
ensuring that changes to the RAM are shadowed to external NVM at appropriate intervals.
All writes that are intended for NVM are written to the RAM, and then are shadowed to the
NVM. Thus, the chip’s internal processors access the RAM only; they do not directly access
either the ROM or external NVM.
The state of the RAM is retained as long as power is applied to the device. After a device
reset, the initialization sequence copies the contents of the ROM and relevant NVM data to
the RAM.
Memory Map
A Neuron C application has a memory map of 64 KB. Figure 6 shows the memory map for a
Series 6000 chip. The memory map is a logical view of device memory, rather than a
physical view, because the Series 6000 chip’s processors only directly access RAM.
The memory map for a Series 6000 chip is “auto-tuned”. That is, the linker decides how to
partition the RAM based on the needs placed upon it by the application. The user does not
specify the address ranges used for each type of memory (code vs data vs persistent data).
24 Hardware Resources