Echelon Series 6000 Chip databook - Manual (Page 65)

2. Configuration data — Information from the Neuron Chip that tells the transceiver
how it is to be set up or configured.
3. Status data — Informational parameters reported from the transceiver to the Neuron
Chip (when requested by the Neuron Chip).
The contents of the configuration data and status data are defined by the transceiver.
The Neuron Chip controls the communication with the transceiver by asserting and
examining status bits. There are four basic operations that the Neuron Chip performs with
the transceiver: transmit packet, receive packet, write configuration, and read status.
When the Neuron Chip wants to transmit a packet, it sets the TX REQ FLAG bit of its
output status field. The transceiver can then accept or reject the request. To reject the
request, the transceiver sets the CLR TX REQ FLAG bit and clears the SET TX FLAG bit.
The transceiver indicates that it is ready to transmit by setting the CLR TX REQ FLAG and
SET TX FLAG bits for one frame. In that same frame, the transceiver must also set the TX
DATA CTS bit to indicate that the Neuron Chip can send the first byte of data.
The Neuron Chip sends a packet of data only if the transceiver accepts the transmit request.
The Neuron Chip then sets the TX FLAG bit for the entire duration of the packet. The
transceiver must set the TX ON bit while it is transmitting a packet.
Each byte is transferred from the Neuron Chip to the transceiver with a handshake protocol.
The transceiver indicates that it is ready to accept a byte by setting the TX DATA CTS bit for
a single frame. The Neuron Chip uses this flag to cause it to send out another byte in a
subsequent frame; the Neuron Chip also sets the TX DATA VALID bit during the frame that
contains the data byte.
After the Neuron Chip sends the last byte in the packet, it clears the TX FLAG bit to indicate
the end of transmission. When the transceiver finishes transmitting the packet, including
any error codes, it must clear the TX ON bit to indicate that it has released the network.
The transceiver can abort transmission if it detects a collision by setting the SET COLL DET
bit for one frame. The Neuron Chip then clears the TX FLAG bit and prepares to resend the
packet.
The transceiver initiates packet reception by setting the RX FLAG bit. The transceiver can
begin sending data to the Neuron Chip in the frame after setting the RX FLAG bit. Each
frame that contains valid data must be marked with the RX DATA VALID bit set. When the
transceiver finishes receiving a packet, it clears the RX FLAG bit and the Neuron Chip
terminates reception of the packet.
The Neuron Chip performs a configuration write or status read by using the TX ADDR R/W
and TX ADDR [2:0] bits. The TX ADDR [2:0] bits indicate which of seven transceiver
registers is being accessed, and the TX ADDR R/W bit indicates whether the operation is a
configuration register write (0) or status register read (1). Register 0 (TX ADDR [2:0] = 000)
is unused, so that TX ADDR R/W = 0 and TX ADDR [2:0] = 000 indicates no read or write
operation is to be performed.
To write to a configuration register, the Neuron Chip clears the TX ADDR R/W bit and
indicates the selected register with the TX ADDR [2:0] bits. The transceiver must
acknowledge that the operation is complete by setting the RD/WR ACK bit. The Neuron
Chip continues to send the configuration write command until it receives a frame with the
RD/WR ACK bit set.
To read a status register, the Neuron Chip sets the TX ADDR R/W bit and indicates the
selected register with the TX ADDR [2:0] bits. The transceiver must acknowledge that the
operation is complete by setting the RD/WR ACK bit and by placing the requested
Series 6000 Chip Data Book 53