Echelon Series 6000 Chip databook - Manual (Page 77)

• LVI circuit trip
• Watchdog timer expiration
• System-level traps
• Software-driven reset
The source of the last reset is saved in the Reset Cause register for diagnostic purposes.
Power-Up and LVI
Both the power-on reset and low-voltage indications act as a single reset source. During
power up sequences, the RST~ pin is held low by the internal LVI until the power supply is
stable. Likewise, when powering down, the RST~ pin is driven low when the power supply
goes below the Series 6000 chip’s minimum operating voltage.
See the FT 6000 Free Topology Smart Transceiver data sheet or the Neuron 6000 Processor
data sheet for internal LVI trip points.
Watchdog Timer
A Series 6000 chip is protected against malfunctioning software or memory faults by three
watchdog timers, one for each processor that makes up the Neuron Core. If the application
or the system software fails to update these timers periodically, the entire Series 6000 chip
automatically resets. The Watchdog Timer circuit is always active and cannot be disabled.
The watchdog timer period is fixed at 840 ms (1.19 Hz) for all system clock rates. However,
the actual timeout range is between 0.8 s and 1.7 s (see Figure 27). Each watchdog timer is
a free-running timer, rather than a one-shot timer; that is, the timeout value is not set or
reset each time the watchdog timer is updated. Updating the watchdog timer ensures that
the expiration of the next timer tick does not cause a processor reset.
Example 1: The top example in Figure 27 shows periodic WDT updates that occur just
before the current WDT tick expires. The update at C ensures that the processor does not
reset at the next WDT tick (which occurs immediately after the update at C). However, the
missed update at D causes the processor to reset. The time between the last WDT update
and the processor reset is about 840 ms.
Example 2: The bottom example in Figure 27 shows periodic WDT updates that occur just
after the current WDT tick has expired. The update at C ensures that the processor does not
reset at the next WDT tick (which occurs almost a full WDT period after C). However, the
missed update at D does not cause the processor to reset because the update at C ensured no
reset. Instead, another WDT period elapses before the processor resets. The time between
the last WDT update and the processor reset is about 1.7 s.
Series 6000 Chip Data Book 65