Echelon Series 6000 Chip databook - Manual (Page 60)

Important: Transmit Enable is actively driven at all times in single-ended mode. In single-
ended mode, the 8 mA driver is connected to CP1 and it is not high impedance when
receiving packets.
At the end of the packet after the Differential Manchester code violation, the Transmit
Enable pin on CP2 is driven low to indicate the end of transmission.
Collision Detection for Single-Ended Mode
As an option, the Neuron Chip accepts an active-low Collision Detect input from the
transceiver. If collision detection is enabled, and CP4 goes low for at least one system clock
period (12.5 ns with an 80 MHz system clock) during transmission, the Neuron Chip is
signaled that a collision has occurred (or is occurring) and that the message must be sent
again. The device then attempts to re-access the channel.
The collision detect flag is checked by firmware at the end of the preamble and end of packet.
If the node does not use collision detection, the only way that it can determine that a
message has not been received is to request an acknowledgment. When acknowledged
service is used, the retry timer is set to allow sufficient time for a message to be sent and
acknowledged (typically 48 ms to 96 ms at 1.25 Mbps when there are no routers in the
transmission path). If the retry timer times out, the device attempts to re-access the
channel. The benefit of using collision detection is that the device does not have to wait for
the retry timer to time-out before attempting to resend the message, because the device
detects the collision when it sends the packet.
Beta 1 and Beta 2 Timeslots in Single-Ended
Mode
Important: The information in this section applies only to development of new network
types. If you use a standard L ON M ARK channel in a L ON W ORKS network, you do not need to
work with the Beta 1 and Beta 2 timeslots.
The idle period between packets comprises the Beta 1 and Beta 2 timeslots. The Beta 1 time
is the fixed component in the idle period after a packet has been sent. This component is a
function of the following:
• Oscillator frequencies and accuracies on the various network devices.
• Media indeterminate time — that time following packet transmission when the
network can appear to be busy due to ringing on the line.
• Minimum interpacket gap — transceiver-dependent timing requirements.
• Receive-end delay — skew between the transmitter Neuron Chip’s and the receiver
Neuron Chip’s view of the end of the packet. This skew can occur because of
buffering in the transceivers, and is typically found in special-purpose mode
transceivers.
The Media Access Control (MAC) Layer timings are a function of five parameters stored in
the configuration data. These parameters determine the Preamble Length, the Packet Cycle,
the Beta 2 Slot Width, the Transmit Interpacket Padding, and the Receive Interpacket
Padding.
All timings are given in terms of the Neuron Chip processor cycles. One cycle is 37.5 ns at 80
MHz, 75 ns at 40 MHz, 150 ns at 20 MHz, 0.3 μs at 10 MHz, and 0.6 μs at 5 MHz:
48 Hardware Resources