Echelon Series 6000 Chip databook - Manual (Page 49)

SVC~
IO0
IO1
IO2
IO3
VDD1V8
IO4
VDD3V3
IO5
IO6
IO7
IO8 VDDPLL
GNDPLL
VOUT1V8
RST~
VIN3V3
VDD3V3
AVDD3V3
CP0
AGND
CP1
NC
GND
IO
9
IO
10
IO
11
VDD
1
V
8
TRST
~
VDD
3
V
3
TCK TMS
TDI
TDO
XIN
XOUT
CP
2
CP
3
CP
4
CS
0
~
VDD
3
V
3
VDD
3
V
3
SDA
_
CS
1
~
VDD
1
V
8
SCL MISO SCK MOSI
37 38 39 40 41 42 43 44 45 46 47 48
1
2
3
4
5
6
7
8
9
10
11
12
13 14 15 16 17 18 19 20 21 22 23 24
25
26
27
28
29
30
31
32
33
34
35
36
Neuron 6000
Processor
®
GND PAD
Figure 9. Neuron 6000 Processor Pinout Diagram
Table 15 lists the pin assignments for the Neuron 6000 Processor. All digital inputs are low-
voltage transistor-transistor logic (LVTTL) compatible, 5 V tolerant, with low leakage. All
digital outputs are slew-rate limited to reduce Electromagnetic Interference (EMI) concerns.
Table 15. Neuron 6000 Processor Pin Assignments
Name
Pin
Number Type Description
SVC~ 1 Digital I/O Service (active low)
IO0 2 Digital I/O IO0 for I/O Objects
IO1 3 Digital I/O IO1 for I/O Objects
IO2 4 Digital I/O IO2 for I/O Objects
IO3 5 Digital I/O IO3 for I/O Objects
VDD1V8 6 Power 1.8 V Power Input
(from internal voltage regulator)
IO4 7 Digital I/O IO4 for I/O Objects
VDD3V3 8 Power 3.3 V Power
IO5 9 Digital I/O IO5 for I/O Objects
Series 6000 Chip Data Book 37