Avoidance of damaging conditions – Echelon Series 6000 Chip databook User Manual

Page 155

•

Connecting individual unused I/O pins directly to GND or to V

. This method is not

recommended in case of software error and because of the possibility of output

declaration to an opposing state.

•

Declaring unused pins as outputs.

Thus, you should never connect a pin that is capable of being configured as an output to

another such pin or directly to GND or to V

Avoidance of Damaging Conditions

All integrated circuit devices can be damaged or destroyed by exceeding specified voltage and

environmental limits. These limits are conservative to ensure reliable operation within the

conditions specified.
The maximum peak temperature for a Series 6000 chip is 260 ºC. See Recommended Solder

Profile, and consult the data sheet of the solder manufacturer for recommendations on the

optimum reflow profile. The actual reflow profile that you choose should consider these peak

temperature limitations.
Most potentially destructive AC waveforms fall into one of two categories:

•

High-voltage (10 kV to 25 kV), low-energy, spikes due to ESD discharge that usually

last no longer than 100 ns. ESD modeling has shown that the human body can

generate and discharge electrostatic voltages of up to 12 kV.

•

Lower-voltage, higher energy, transients that can last for several hundred

microseconds or more, that can be caused by capacitive coupling of lightning or by

inductive load sources.

Different protection devices for these destructive waveforms must be implemented,

depending on what is anticipated in the operating environment. Failure modes can be

quantified and protective precautions taken to avoid product malfunction. This could be PC

board layout-related or could involve the use of external protection devices. External

protection is required for products that are subject to human contact or where interfaces to

other equipment might be encountered. See Chapter 4, Design and Test for Electromagnetic

Compatibility, for more information about ESD protection.
Many factors, including ambient temperature and semiconductor lot-to-lot processing

variations, can influence the effect of illegal conditions on a Series 6000 chip. The ground

pins are internally connected to the substrate of the silicon die and are the reference point

for all voltages. The Series 6000 chip functions for V

are connected to the positive supply

pins. In limited temperature range environments, the device might operate over a wider V

ranges, with timing, drive, FT transceiver, and other specifications not met. There might

also be some adverse effects on gate oxides from long-term exposures to V

greater than 3.3

V.
For Series 6000 chips, do not connect an external 1.8 V source to any of the VDD1V8 pins (6,

16, and 44). Connect these pins to the VOUT1V8 pin (27) only. Using an external 1.8 V

source voids the warranty for the chip, and can cause unpredictable and possibly

irreparable results.
Two additional damage mechanisms that are resident in CMOS chips include zap and latch-

up:

•

Zap refers to damage caused by exposure to very-high-voltage static electricity. This

damage usually appears as breakdown of the relatively thin oxide layers, which

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