Echelon Series 6000 Chip databook - Manual (Page 158)

• Use short, low-inductance, traces for the analog circuitry to reduce inductive,
capacitive, and radio frequency (RF) noise sensitivities.
• Use short, low-inductance, traces for the digital circuitry to reduce inductive,
capacitive, and radio frequency (RF) radiated noise.
• Connect bypass capacitors between the V
DD
and GND pairs with minimal trace
length. These capacitors help supply the instantaneous currents of the digital
circuitry, in addition to decoupling the noise that can be generated by other sections
of the device or by other circuitry on the power supply.
• Use short, wide, low-inductance, traces to connect all of the GND ground pins
together. Depending on the application, a double-sided PCB with a ground plane
under the device that connects all of the digital and analog GND pins together could
be a good grounding method. A multilayer PCB with a ground plane that connects
all of the digital and analog GND pins together would be the optimal ground
configuration. These methods result in the lowest resistance and the lowest
inductance in the ground circuit, which is important to reduce voltage spikes in the
ground circuit resulting from the high-speed digital current spikes. Suppressing
these voltage spikes on the integrated circuit is the reason for multiple GND leads.
• Use short, wide, low-inductance, traces to connect all of the V
DD
power supply pins
together. Depending on the application, a double-sided PCB with V
DD
bypass
capacitors to the ground plane under the device can complete the low-impedance
coupling for the power supply. For a multilayer PCB with a power plane, connecting
all of the digital and analog V
DD
pins to the power plane would be the optimal power
distribution method. The integrated circuit layout and packaging considerations for
the 3.3 V
DD
power circuit are essentially the same as for the ground circuit.
Decoupling Capacitors
To absorb switching spikes, which can introduce noise problems, the following CMOS devices
should be bypassed with good quality 0.022 μF to 0.33 μF decoupling capacitors:
• Every device that drives a bus on which outputs switch simultaneously.
• All synchronous counters.
• Devices used as oscillator elements.
• Schmitt-trigger devices with slow input rise and fall times. The slower the rise and
fall time, the larger the bypass capacitor. Lab experimentation is suggested.
Bypass capacitors should be distributed over the circuit board. In addition, boards could be
decoupled with a 1 μF capacitor. You should also ensure low-impedance paths to and from
logic devices in board layouts.
Board Soldering Considerations
This section describes PC board soldering considerations for design and manufacturing of
Series 6000 devices.
Recommended Solder Profile
Follow the general guidelines described in IPC/JEDEC Standard J-STD-020D.1 when
soldering Series 6000 chips to PCBs. This standard includes information for classification
reflow profiles. All Series 6000 chips comply with the European Union Restriction of
146 Handling and Manufacturing Guidelines