Feature control error status register, Quadlet offset format_7 mode_0, Quadlet offset format_7 mode_1 – ALLIED Vision Technologies Pike F-1600 User Manual
Page 323: Format_7 control and status register (csr), Table 149: format_7 control and status register

Configuration of the camera
PIKE Technical Manual V5.1.2
323
Feature control error status register
Video mode control and status registers for
Format_7
Quadlet offset Format_7 Mode_0
The quadlet offset to the base address for Format_7 Mode_0, which can be read
out at F0F002E0h (according to
Table 142: Frame rate inquiry register
303) gives 003C2000h.
4 x 3C2000h = F08000h so that the base address for the latter (
Format_7 control and status register
F0000000h + F08000h = F0F08000h.
Quadlet offset Format_7 Mode_1
The quadlet offset to the base address for Format_7 Mode_1, which can be read
out at F0F002E4h (according to
Table 142: Frame rate inquiry register
303) gives 003C2400h.
4 x 003C2400h = F09000h so that the base address for the latter (
Format_7 control and status register
F0000000h + F09000h = F0F09000h.
Format_7 control and status register (CSR)
Offset
Name
Notes
640h
Feature_Control_Error_Status_HI
Always 0
644h
Feature_Control_Error_Status_LO
Always 0
Table 148: Feature control error register
Offset
Name
Notes
000h
MAX_IMAGE_SIZE_INQ
According to IIDC V1.31
004h
UNIT_SIZE_INQ
According to IIDC V1.31
008h
IMAGE_POSITION
According to IIDC V1.31
00Ch
IMAGE_SIZE
According to IIDC V1.31
010h
COLOR_CODING_ID
See note
014h
COLOR_CODING_INQ
According to IIDC V1.31
Table 149: Format_7 control and status register