Rainbow Electronics ATmega64C1 User Manual

Features

Table of contents

Document Outline

Features
1. Pin Configurations
- 1.1 Pin Descriptions
2. Overview
- 2.1 Block Diagram
- 2.2 Automotive Quality Grade
- 2.3 Pin Descriptions
- 2.4 About Code Examples
3. AVR CPU Core
- 3.1 Introduction
- 3.2 Architectural Overview
- 3.3 ALU - Arithmetic Logic Unit
- 3.4 Status Register
- 3.5 General Purpose Register File
  - 3.5.1 The X-register, Y-register, and Z-register
- 3.6 Stack Pointer
- 3.7 Instruction Execution Timing
- 3.8 Reset and Interrupt Handling
  - 3.8.1 Interrupt Behavior
  - 3.8.2 Interrupt Response Time
4. Memories
- 4.1 In-System Reprogrammable Flash Program Memory
- 4.2 SRAM Data Memory
  - 4.2.1 SRAM Data Access Times
- 4.3 EEPROM Data Memory
- 4.4 I/O Memory
- 4.5 General Purpose I/O Registers
5. System Clock
- 5.1 Clock Systems and their Distribution
- 5.2 Clock Sources
- 5.3 Default Clock Source
- 5.4 Low Power Crystal Oscillator
- 5.5 Calibrated Internal RC Oscillator
  - 5.5.1 Oscillator Calibration Register - OSCCAL
- 5.6 PLL
  - 5.6.1 Internal PLL
  - 5.6.2 PLL Control and Status Register - PLLCSR
- 5.7 128 kHz Internal Oscillator
- 5.8 External Clock
- 5.9 Clock Output Buffer
- 5.10 System Clock Prescaler
  - 5.10.1 Clock Prescaler Register - CLKPR
6. Power Management and Sleep Modes
- 6.1 Sleep Mode Control Register
  - 6.1.1 Sleep Mode Control Register - SMCR
- 6.2 Idle Mode
- 6.3 ADC Noise Reduction Mode
- 6.4 Power-down Mode
- 6.5 Standby Mode
- 6.6 Power Reduction Register
  - 6.6.1 Power Reduction Register - PRR
- 6.7 Minimizing Power Consumption
7. System Control and Reset
- 7.1 Resetting the AVR
- 7.2 Reset Sources
- 7.3 Internal Voltage Reference
  - 7.3.1 Voltage Reference Enable Signals and Start-up Time
  - 7.3.2 Voltage Reference Characteristics
- 7.4 Watchdog Timer
  - 7.4.1 Watchdog Timer Control Register - WDTCSR
8. Interrupts
- 8.1 Interrupt Vectors in ATmega32/64/M1/C1
  - 8.1.1 Moving Interrupts Between Application and Boot Space
  - 8.1.2 MCU Control Register - MCUCR
9. I/O-Ports
- 9.1 Introduction
- 9.2 Ports as General Digital I/O
- 9.3 Alternate Port Functions
- 9.4 Register Description for I/O-Ports
10. External Interrupts
- 10.1 Pin Change Interrupt Timing
- 10.2 External Interrupt Control Register A - EICRA
11. Timer/Counter0 and Timer/Counter1 Prescalers
- 11.1 Internal Clock Source
- 11.2 Prescaler Reset
- 11.3 External Clock Source
  - 11.3.1 General Timer/Counter Control Register - GTCCR
12. 8-bit Timer/Counter0 with PWM
- 12.1 Overview
  - 12.1.1 Definitions
  - 12.1.2 Registers
- 12.2 Timer/Counter Clock Sources
- 12.3 Counter Unit
- 12.4 Output Compare Unit
- 12.5 Compare Match Output Unit
  - 12.5.1 Compare Output Mode and Waveform Generation
- 12.6 Modes of Operation
- 12.7 Timer/Counter Timing Diagrams
- 12.8 8-bit Timer/Counter Register Description
13. 16-bit Timer/Counter1 with PWM
- 13.1 Overview
  - 13.1.1 Registers
  - 13.1.2 Definitions
- 13.2 Accessing 16-bit Registers
  - 13.2.1 Reusing the Temporary High Byte Register
- 13.3 Timer/Counter Clock Sources
- 13.4 Counter Unit
- 13.5 Input Capture Unit
- 13.6 Output Compare Units
- 13.7 Compare Match Output Unit
  - 13.7.1 Compare Output Mode and Waveform Generation
- 13.8 Modes of Operation
- 13.9 Timer/Counter Timing Diagrams
- 13.10 16-bit Timer/Counter Register Description
14. Power Stage Controller - (PSC) (only ATmega32/64M1)
- 14.1 Features
- 14.2 Overview
- 14.3 Accessing 16-bit Registers
- 14.4 PSC Description
- 14.5 Functional Description
- 14.6 Update of Values
  - 14.6.1 Value Update Synchronization
- 14.7 Overlap Protection
- 14.8 Signal Description
  - 14.8.1 Input Description
  - 14.8.2 Output Description
- 14.9 PSC Input
  - 14.9.1 PSC Input Configuration
- 14.10 PSC Input Modes 001b to 10xb: Deactivate outputs without changing timing.
- 14.11 PSC Input Mode 11xb: Halt PSC and Wait for Software Action
- 14.12 Analog Synchronization
- 14.13 Interrupt Handling
- 14.14 PSC Clock Sources
- 14.15 Interrupts
  - 14.15.1 Interrupt Vector
  - 14.15.2 PSC Interrupt Vectors in ATmega32/64/M1/C1
- 14.16 PSC Register Definition
15. Serial Peripheral Interface - SPI
- 15.1 Features
- 15.2 SS Pin Functionality
- 15.3 Data Modes
16. Controller Area Network - CAN
- 16.1 Features
- 16.2 CAN Protocol
- 16.3 CAN Controller
- 16.4 CAN Channel
- 16.5 Message Objects
- 16.6 CAN Timer
- 16.7 Error Management
- 16.8 Interrupts
  - 16.8.1 Interrupt organization
  - 16.8.2 Interrupt Behavior
- 16.9 CAN Register Description
- 16.10 General CAN Registers
- 16.11 MOb Registers
- 16.12 Examples of CAN Baud Rate Setting
17. LIN / UART - Local Interconnect Network Controller or UART
- 17.1 LIN Features
- 17.2 UART Features
- 17.3 LIN Protocol
- 17.4 LIN / UART Controller
- 17.5 LIN / UART Description
- 17.6 LIN / UART Register Description
18. Analog to Digital Converter - ADC
- 18.1 Features
- 18.2 Operation
- 18.3 Starting a Conversion
- 18.4 Prescaling and Conversion Timing
- 18.5 Changing Channel or Reference Selection
  - 18.5.1 ADC Input Channels
  - 18.5.2 ADC Voltage Reference
- 18.6 ADC Noise Canceler
- 18.7 ADC Conversion Result
- 18.8 Temperature Measurement
  - 18.8.1 User Calibration
  - 18.8.2 Manufacturing Calibration
- 18.9 ADC Register Description
- 18.10 Amplifier
- 18.11 Amplifier Control Registers
19. ISRC - Current Source
- 19.1 Features
- 19.2 Typical applications
- 19.3 Control Register
  - 19.3.1 ADC Control and Status Register B- ADCSRB
20. Analog Comparator
- 20.1 Features
- 20.2 Overview
- 20.3 Use of ADC Amplifiers
- 20.4 Analog Comparator Register Description
21. Digital to Analog Converter - DAC
- 21.1 Features
- 21.2 Operation
- 21.3 Starting a Conversion
  - 21.3.1 DAC Voltage Reference
- 21.4 DAC Register Description
  - 21.4.1 Digital to Analog Conversion Control Register - DACON
  - 21.4.2 Digital to Analog Converter input Register - DACH and DACL
    - 21.4.2.1 DALA = 0
    - 21.4.2.2 DALA = 1
22. debugWIRE On-chip Debug System
- 22.1 Features
- 22.2 Overview
- 22.3 Physical Interface
- 22.4 Software Break Points
- 22.5 Limitations of debugWIRE
- 22.6 debugWIRE Related Register in I/O Memory
  - 22.6.1 debugWire Data Register - DWDR
23. Boot Loader Support - Read-While-Write Self-Programming ATmega32/64/M1/C1
- 23.1 Boot Loader Features
- 23.2 Application and Boot Loader Flash Sections
  - 23.2.1 Application Section
  - 23.2.2 BLS - Boot Loader Section
- 23.3 Read-While-Write and No Read-While-Write Flash Sections
  - 23.3.1 RWW - Read-While-Write Section
  - 23.3.2 NRWW - No Read-While-Write Section
- 23.4 Boot Loader Lock Bits
- 23.5 Entering the Boot Loader Program
  - 23.5.1 Store Program Memory Control and Status Register - SPMCSR
- 23.6 Addressing the Flash During Self-Programming
- 23.7 Self-Programming the Flash
24. Memory Programming
- 24.1 Program And Data Memory Lock Bits
- 24.2 Fuse Bits
- 24.3 PSC Output Behavior During Reset
  - 24.3.1 Latching of Fuses
- 24.4 Signature Bytes
  - 24.4.1 Signature Bytes
- 24.5 Calibration Byte
- 24.6 Parallel Programming Parameters, Pin Mapping, and Commands
  - 24.6.1 Signal Names
- 24.7 Serial Programming Pin Mapping
- 24.8 Parallel Programming
- 24.9 Serial Downloading
25. Electrical Characteristics
- 25.1 Absolute Maximum Ratings*
- 25.2 DC Characteristics
- 25.3 Clock Characteristics
  - 25.3.1 Calibrated Internal RC Oscillator Accuracy
- 25.4 External Clock Drive Characteristics
- 25.5 Maximum Speed vs. VCC
- 25.6 PLL Characteristics
- 25.7 SPI Timing Characteristics
- 25.8 ADC Characteristics
- 25.9 Parallel Programming Characteristics
26. ATmega32/64/M1/C1 Typical Characteristics
- 26.1 Active Supply Current
- 26.2 Idle Supply Current
  - 26.2.1 Using the Power Reduction Register
- 26.3 Power-Down Supply Current
- 26.4 Standby Supply Current
- 26.5 Pin Pull-up
- 26.6 Pin Driver Strength
- 26.7 Pin Thresholds and Hysteresis
- 26.8 BOD Thresholds and Analog Comparator Hysterisis
- 26.9 Analog Reference
- 26.10 Internal Oscillator Speed
- 26.11 Current Consumption of Peripheral Units
- 26.12 Current Consumption in Reset and Reset Pulse width
27. Register Summary
28. Instruction Set Summary
29. Errata
- 29.1 Errata Summary
  - 29.1.1 ATmega32/64/M1/C1 Rev. A (Mask Revision)
- 29.2 Errata Description
30. Ordering Information
31. Package Information
- 31.1 TQFP32
- 31.2 QFN32
32. Datasheet Revision History for ATmega32/64/M1/C1
- 32.1 7647A