Rainbow Electronics ATmega64C1 - Manual (Page 195)

195
7647A–AVR–02/08
ATmega32/64/M1/C1
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
Detection of more than five consecutive bits with the same polarity. This flag can generate an
interrupt.
• Bit 2 – CERR: CRC Error
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
The receiver performs a CRC check on every de-stuffed received message from the start of
frame up to the data field. If this checking does not match with the de-stuffed CRC field, a CRC
error is set.
• Bit 1 – FERR: Form Error
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
The form error results from one or more violations of the fixed form in the following bit fields:
• CRC delimiter.
• Acknowledgment delimiter.
• EOF
• Bit 0 – AERR: Acknowledgment Error
This flag can generate an interrupt. It must be cleared using a read-modify-write software routine
on the whole CANSTMOB register.
No detection of the dominant bit in the acknowledge slot.
16.11.2 CAN MOb Control and DLC Register - CANCDMOB
• Bit 7:6 – CONMOB1:0: Configuration of Message Object
These bits set the communication to be performed (no initial value after RESET).
– 00 - disable.
– 01 - enable transmission.
– 10 - enable reception.
– 11 - enable frame buffer reception
These bits are not cleared once the communication is performed. The user must re-write the
configuration to enable a new communication.
• This operation is necessary to be able to reset the BXOK flag.
• This operation also set the corresponding bit in the CANEN registers.
• Bit 5 – RPLV: Reply Valid
Used in the automatic reply mode after receiving a remote frame.
Bit 7 6 5 4 3 2 1 0
CONMOB1 CONMOB0 RPLV IDE DLC3 DLC2 DLC1 DLC0 CANCDMOB
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value - - - - - - - -