Rainbow Electronics ATmega64C1 - Manual (Page 186)

186
7647A–AVR–02/08
ATmega32/64/M1/C1
– 0 - standby mode: The on-going transmission (if exists) is normally terminated and the
CAN channel is frozen (the CONMOB bits of every MOb do not change). The transmitter
constantly provides a recessive level. In this mode, the receiver is not enabled but all the
registers and mailbox remain accessible from CPU. In this mode, the receiver is not
enabled but all the registers and mailbox remain accessible from CPU.
Note:A standby mode applied during a reception may corrupt the on-going reception or set the
controller in a wrong state. The controller will restart correctly from this state if a software
reset (SWRES) is applied. If no reset is considered, a possible solution is to wait for a
lake of a receiver busy (RXBSY) before to enter in stand-by mode. The best solution is
first to apply an abort request command (ABRQ) and then wait for the lake of the receiver
busy (RXBSY) before to enter in stand-by mode. In any cases, this standby mode behav-
ior has no effect on the CAN bus integrity.
– 1 - enable mode: The CAN channel enters in enable mode once 11 recessive bits
has been read.
• Bit 0 – SWRES: Software Reset Request
This auto resettable bit only resets the CAN controller.
– 0 - no reset
– 1 - reset: this reset is “ORed” with the hardware reset.
16.10.2 CAN General Status Register - CANGSTA
• Bit 7 – Reserved Bit
This bit is reserved for future use.
• Bit 6 – OVRG: Overload Frame Flag
This flag does not generate an interrupt.
– 0 - no overload frame.
– 1 - overload frame: set by hardware as long as the produced overload frame is sent.
• Bit 5 – Reserved Bit
This bit is reserved for future use.
• Bit 4 – TXBSY: Transmitter Busy
This flag does not generate an interrupt.
– 0 - transmitter not busy.
– 1 - transmitter busy: set by hardware as long as a frame (data, remote, overload or
error frame) or an ACK field is sent. Also set when an inter frame space is sent.
• Bit 3 – RXBSY: Receiver Busy
This flag does not generate an interrupt.
– 0 - receiver not busy
– 1 - receiver busy: set by hardware as long as a frame is received or monitored.
Bit 7 6 5 4 3 2 1 0
- OVRG - TXBSY RXBSY ENFG BOFF ERRP CANGSTA
Read/Write - R - R R R R R
Initial Value - 0 - 0 0 0 0 0