Rainbow Electronics ATmega64C1 User Manual
Features
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Features
•
High Performance, Low Power AVR ® 8-bit Microcontroller
•
Advanced RISC Architecture
– 131 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1 MIPS throughput per MHz
– On-chip 2-cycle Multiplier
•
Data and Non-Volatile Program Memory
– 32K/64K Bytes Flash of In-System Programmable Program Memory
• Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
– In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– 1024/2048 Bytes of In-System Programmable EEPROM
• Endurance: 50,000 Write/Erase Cycles
•
Programming Lock for Flash Program and EEPROM Data Security
•
2048/4096 Bytes Internal SRAM
•
On Chip Debug Interface (debugWIRE)
•
Peripheral Features
– One 12-bit High Speed PSC (Power Stage Controller) (only ATmega32/64M1)
• Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time
• Variable PWM duty Cycle and Frequency
• Synchronous Update of all PWM Registers
• Auto Stop Function for Emergency Event
– One 8-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode
and Capture Mode
– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare
Mode and Capture Mode
– CAN 2.0A/B with 6 Message Objects
– LIN 2.1 and 1.3 Controller or 8-Bit UART
– One Master/Slave SPI Serial Interface
– 10-bit ADC
• Up To 11 Single Ended Channels and 3 Fully Differential ADC Channel Pairs
• Programmable Gain (5x, 10x, 20x, 40x) on Differential Channels
• Internal Reference Voltage
• Direct Power Supply Voltage Measurement
– 10-bit DAC for Variable Voltage Reference (Comparators, ADC)
– Four Analog Comparators with Variable Threshold Detection
– 100µA ±2% Current Source (LIN Node Identification)
– Interrupt and Wake-up on Pin Change
– Programmable Watchdog Timer with Separate On-Chip Oscillator
– On-chipTemperature Sensor
•
Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power Down Modes
– Power On Reset and Programmable Brown Out Detection
– In-System Programmable via SPI Port
– High Precision Crystal Oscillator for CAN Operations (16 MHz)
– Internal Calibrated RC Oscillator ( 8 MHz)
7647A–AVR–02/08
8-bit
M
icrocontroller
with 32K/64K
Bytes In-System
Programmable
Flas
h
ATmega32M1
ATmega64M1
ATmega32C1
ATmega64C1
Preliminary
Document Outline
- Features
- 1. Pin Configurations
- 2. Overview
- 3. AVR CPU Core
- 4. Memories
- 5. System Clock
- 6. Power Management and Sleep Modes
- 7. System Control and Reset
- 8. Interrupts
- 9. I/O-Ports
- 9.1 Introduction
- 9.2 Ports as General Digital I/O
- 9.3 Alternate Port Functions
- 9.4 Register Description for I/O-Ports
- 9.4.1 Port B Data Register - PORTB
- 9.4.2 Port B Data Direction Register - DDRB
- 9.4.3 Port B Input Pins Address - PINB
- 9.4.4 Port C Data Register - PORTC
- 9.4.5 Port C Data Direction Register - DDRC
- 9.4.6 Port C Input Pins Address - PINC
- 9.4.7 Port D Data Register - PORTD
- 9.4.8 Port D Data Direction Register - DDRD
- 9.4.9 Port D Input Pins Address - PIND
- 9.4.10 Port E Data Register - PORTE
- 9.4.11 Port E Data Direction Register - DDRE
- 9.4.12 Port E Input Pins Address - PINE
- 10. External Interrupts
- 10.1 Pin Change Interrupt Timing
- 10.2 External Interrupt Control Register A - EICRA
- 10.2.1 External Interrupt Mask Register - EIMSK
- 10.2.2 External Interrupt Flag Register - EIFR
- 10.2.3 Pin Change Interrupt Control Register - PCICR
- 10.2.4 Pin Change Interrupt Flag Register - PCIFR
- 10.2.5 Pin Change Mask Register 3 - PCMSK3
- 10.2.6 Pin Change Mask Register 2 - PCMSK2
- 10.2.7 Pin Change Mask Register 1 - PCMSK1
- 10.2.8 Pin Change Mask Register 0 - PCMSK0
- 11. Timer/Counter0 and Timer/Counter1 Prescalers
- 12. 8-bit Timer/Counter0 with PWM
- 12.1 Overview
- 12.2 Timer/Counter Clock Sources
- 12.3 Counter Unit
- 12.4 Output Compare Unit
- 12.5 Compare Match Output Unit
- 12.6 Modes of Operation
- 12.7 Timer/Counter Timing Diagrams
- 12.8 8-bit Timer/Counter Register Description
- 12.8.1 Timer/Counter Control Register A - TCCR0A
- 12.8.2 Timer/Counter Control Register B - TCCR0B
- 12.8.3 Timer/Counter Register - TCNT0
- 12.8.4 Output Compare Register A - OCR0A
- 12.8.5 Output Compare Register B - OCR0B
- 12.8.6 Timer/Counter Interrupt Mask Register - TIMSK0
- 12.8.7 Timer/Counter 0 Interrupt Flag Register - TIFR0
- 13. 16-bit Timer/Counter1 with PWM
- 13.1 Overview
- 13.2 Accessing 16-bit Registers
- 13.3 Timer/Counter Clock Sources
- 13.4 Counter Unit
- 13.5 Input Capture Unit
- 13.6 Output Compare Units
- 13.7 Compare Match Output Unit
- 13.8 Modes of Operation
- 13.9 Timer/Counter Timing Diagrams
- 13.10 16-bit Timer/Counter Register Description
- 13.10.1 Timer/Counter1 Control Register A - TCCR1A
- 13.10.2 Timer/Counter1 Control Register B - TCCR1B
- 13.10.3 Timer/Counter1 Control Register C - TCCR1C
- 13.10.4 Timer/Counter1 - TCNT1H and TCNT1L
- 13.10.5 Output Compare Register 1 A - OCR1AH and OCR1AL
- 13.10.6 Output Compare Register 1 B - OCR1BH and OCR1BL
- 13.10.7 Input Capture Register 1 - ICR1H and ICR1L
- 13.10.8 Timer/Counter1 Interrupt Mask Register - TIMSK1
- 13.10.9 Timer/Counter1 Interrupt Flag Register - TIFR1
- 14. Power Stage Controller - (PSC) (only ATmega32/64M1)
- 14.1 Features
- 14.2 Overview
- 14.3 Accessing 16-bit Registers
- 14.4 PSC Description
- 14.5 Functional Description
- 14.6 Update of Values
- 14.7 Overlap Protection
- 14.8 Signal Description
- 14.9 PSC Input
- 14.10 PSC Input Modes 001b to 10xb: Deactivate outputs without changing timing.
- 14.11 PSC Input Mode 11xb: Halt PSC and Wait for Software Action
- 14.12 Analog Synchronization
- 14.13 Interrupt Handling
- 14.14 PSC Clock Sources
- 14.15 Interrupts
- 14.16 PSC Register Definition
- 14.16.1 PSC Output Configuration - POC
- 14.16.2 PSC Synchro Configuration - PSYNC
- 14.16.3 PSC Output Compare SA Register - POCRnSAH and POCRnSAL
- 14.16.4 PSC Output Compare RA Register - POCRnRAH and POCRnRAL
- 14.16.5 PSCOutput Compare SB Register - POCRnSBH and POCRnSBL
- 14.16.6 PSC Output Compare RB Register - POCR_RBH and POCR_RBL
- 14.16.7 PSC Configuration Register - PCNF
- 14.16.8 PSC Control Register - PCTL
- 14.16.9 PSC Module n Input Control Register - PMICn
- 14.16.10 PSC Interrupt Mask Register - PIM
- 14.16.11 PSC Interrupt Flag Register - PIFR
- 15. Serial Peripheral Interface - SPI
- 16. Controller Area Network - CAN
- 16.1 Features
- 16.2 CAN Protocol
- 16.2.1 Principles
- 16.2.2 Message Formats
- 16.2.3 CAN Bit Timing
- 16.2.3.1 Bit Construction
- 16.2.3.2 Synchronization Segment
- 16.2.3.3 Propagation Time Segment
- 16.2.3.4 Phase Segment 1
- 16.2.3.5 Sample Point
- 16.2.3.6 Phase Segment 2
- 16.2.3.7 Information Processing Time
- 16.2.3.8 Bit Lengthening
- 16.2.3.9 Bit Shortening
- 16.2.3.10 Synchronization Jump Width
- 16.2.3.11 Programming the Sample Point
- 16.2.3.12 Synchronization
- 16.2.4 Arbitration
- 16.2.5 Errors
- 16.3 CAN Controller
- 16.4 CAN Channel
- 16.5 Message Objects
- 16.6 CAN Timer
- 16.7 Error Management
- 16.8 Interrupts
- 16.9 CAN Register Description
- 16.10 General CAN Registers
- 16.10.1 CAN General Control Register - CANGCON
- 16.10.2 CAN General Status Register - CANGSTA
- 16.10.3 CAN General Interrupt Register - CANGIT
- 16.10.4 CAN General Interrupt Enable Register - CANGIE
- 16.10.5 CAN Enable MOb Registers - CANEN2 and CANEN1
- 16.10.6 CAN Enable Interrupt MOb Registers - CANIE2 and CANIE1
- 16.10.7 CAN Status Interrupt MOb Registers - CANSIT2 and CANSIT1
- 16.10.8 CAN Bit Timing Register 1 - CANBT1
- 16.10.9 CAN Bit Timing Register 2 - CANBT2
- 16.10.10 CAN Bit Timing Register 3 - CANBT3
- 16.10.11 CAN Timer Control Register - CANTCON
- 16.10.12 CAN Timer Registers - CANTIML and CANTIMH
- 16.10.13 CAN TTC Timer Registers - CANTTCL and CANTTCH
- 16.10.14 CAN Transmit Error Counter Register - CANTEC
- 16.10.15 CAN Receive Error Counter Register - CANREC
- 16.10.16 CAN Highest Priority MOb Register - CANHPMOB
- 16.10.17 CAN Page MOb Register - CANPAGE
- 16.11 MOb Registers
- 16.11.1 CAN MOb Status Register - CANSTMOB
- 16.11.2 CAN MOb Control and DLC Register - CANCDMOB
- 16.11.3 CAN Identifier Tag Registers - CANIDT1, CANIDT2, CANIDT3, and CANIDT4
- 16.11.4 CAN Identifier Mask Registers - CANIDM1, CANIDM2, CANIDM3, and CANIDM4
- 16.11.5 CAN Time Stamp Registers - CANSTML and CANSTMH
- 16.11.6 CAN Data Message Register - CANMSG
- 16.12 Examples of CAN Baud Rate Setting
- 17. LIN / UART - Local Interconnect Network Controller or UART
- 17.1 LIN Features
- 17.2 UART Features
- 17.3 LIN Protocol
- 17.4 LIN / UART Controller
- 17.5 LIN / UART Description
- 17.5.1 Reset
- 17.5.2 Clock
- 17.5.3 LIN Protocol Selection
- 17.5.4 Configuration
- 17.5.5 Busy Signal
- 17.5.6 Bit Timing
- 17.5.7 Data Length
- 17.5.8 xxOK Flags
- 17.5.9 xxERR Flags
- 17.5.10 Frame Time Out
- 17.5.11 Break-in-data
- 17.5.12 Checksum
- 17.5.13 Interrupts
- 17.5.14 Message Filtering
- 17.5.15 Data Management
- 17.5.16 OCD Support
- 17.6 LIN / UART Register Description
- 17.6.1 LIN Control Register - LINCR
- 17.6.2 LIN Status and Interrupt Register - LINSIR
- 17.6.3 LIN Enable Interrupt Register - LINENIR
- 17.6.4 LIN Error Register - LINERR
- 17.6.5 LIN Bit Timing Register - LINBTR
- 17.6.6 LIN Baud Rate Register - LINBRR
- 17.6.7 LIN Data Length Register - LINDLR
- 17.6.8 LIN Identifier Register - LINIDR
- 17.6.9 LIN Data Buffer Selection Register - LINSEL
- 17.6.10 LIN Data Register - LINDAT
- 18. Analog to Digital Converter - ADC
- 18.1 Features
- 18.2 Operation
- 18.3 Starting a Conversion
- 18.4 Prescaling and Conversion Timing
- 18.5 Changing Channel or Reference Selection
- 18.6 ADC Noise Canceler
- 18.7 ADC Conversion Result
- 18.8 Temperature Measurement
- 18.9 ADC Register Description
- 18.10 Amplifier
- 18.11 Amplifier Control Registers
- 19. ISRC - Current Source
- 20. Analog Comparator
- 20.1 Features
- 20.2 Overview
- 20.3 Use of ADC Amplifiers
- 20.4 Analog Comparator Register Description
- 20.4.1 Analog Comparator 0 Control Register - AC0CON
- 20.4.2 Analog Comparator 1Control Register - AC1CON
- 20.4.3 Analog Comparator 2 Control Register - AC2CON
- 20.4.4 Analog Comparator 3 Control Register - AC3CON
- 20.4.5 Analog Comparator Status Register - ACSR
- 20.4.6 Digital Input Disable Register 0 - DIDR0
- 20.4.7 Digital Input Disable Register 1- DIDR1
- 21. Digital to Analog Converter - DAC
- 22. debugWIRE On-chip Debug System
- 23. Boot Loader Support - Read-While-Write Self-Programming ATmega32/64/M1/C1
- 23.1 Boot Loader Features
- 23.2 Application and Boot Loader Flash Sections
- 23.3 Read-While-Write and No Read-While-Write Flash Sections
- 23.4 Boot Loader Lock Bits
- 23.5 Entering the Boot Loader Program
- 23.6 Addressing the Flash During Self-Programming
- 23.7 Self-Programming the Flash
- 23.7.1 Performing Page Erase by SPM
- 23.7.2 Filling the Temporary Buffer (Page Loading)
- 23.7.3 Performing a Page Write
- 23.7.4 Using the SPM Interrupt
- 23.7.5 Consideration While Updating BLS
- 23.7.6 Prevent Reading the RWW Section During Self-Programming
- 23.7.7 Setting the Boot Loader Lock Bits by SPM
- 23.7.8 EEPROM Write Prevents Writing to SPMCSR
- 23.7.9 Reading the Fuse and Lock Bits from Software
- 23.7.10 Reading the Signature Row from Software
- 23.7.11 Preventing Flash Corruption
- 23.7.12 Programming Time for Flash when Using SPM
- 23.7.13 Simple Assembly Code Example for a Boot Loader
- 23.7.14 ATmega32/64/M1/C1 - 32K -Flash Boot Loader Parameters
- 23.7.15 ATmega32/64/M1/C1 - 64K - Flash Boot Loader Parameters
- 24. Memory Programming
- 24.1 Program And Data Memory Lock Bits
- 24.2 Fuse Bits
- 24.3 PSC Output Behavior During Reset
- 24.4 Signature Bytes
- 24.5 Calibration Byte
- 24.6 Parallel Programming Parameters, Pin Mapping, and Commands
- 24.7 Serial Programming Pin Mapping
- 24.8 Parallel Programming
- 24.8.1 Enter Programming Mode
- 24.8.2 Considerations for Efficient Programming
- 24.8.3 Chip Erase
- 24.8.4 Programming the Flash
- 24.8.5 Programming the EEPROM
- 24.8.6 Reading the Flash
- 24.8.7 Reading the EEPROM
- 24.8.8 Programming the Fuse Low Bits
- 24.8.9 Programming the Fuse High Bits
- 24.8.10 Programming the Extended Fuse Bits
- 24.8.11 Programming the Lock Bits
- 24.8.12 Reading the Fuse and Lock Bits
- 24.8.13 Reading the Signature Bytes
- 24.8.14 Reading the Calibration Byte
- 24.8.15 Parallel Programming Characteristics
- 24.9 Serial Downloading
- 25. Electrical Characteristics
- 26. ATmega32/64/M1/C1 Typical Characteristics
- 26.1 Active Supply Current
- 26.2 Idle Supply Current
- 26.3 Power-Down Supply Current
- 26.4 Standby Supply Current
- 26.5 Pin Pull-up
- 26.6 Pin Driver Strength
- 26.7 Pin Thresholds and Hysteresis
- 26.8 BOD Thresholds and Analog Comparator Hysterisis
- 26.9 Analog Reference
- 26.10 Internal Oscillator Speed
- 26.11 Current Consumption of Peripheral Units
- 26.12 Current Consumption in Reset and Reset Pulse width
- 27. Register Summary
- 28. Instruction Set Summary
- 29. Errata
- 30. Ordering Information
- 31. Package Information
- 32. Datasheet Revision History for ATmega32/64/M1/C1