2 timer/counter control register b - tccr0b – Rainbow Electronics ATmega64C1 User Manual
Page 102
102
7647A–AVR–02/08
ATmega32/64/M1/C1
shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to phase cor-
rect PWM mode.
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the ATmega32/64/M1/C1 and will always read as zero.
• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-
form generation to be used, see
. Modes of operation supported by the Timer/Counter
unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of
Pulse Width Modulation (PWM) modes (see
“Modes of Operation” on page 94
Notes:
1. MAX = 0xFF
2. BOTTOM = 0x00
12.8.2
Timer/Counter Control Register B – TCCR0B
Table 12-7.
Compare Output Mode, Phase Correct PWM Mode
COM0B1
COM0B0
Description
0
0
Normal port operation, OC0B disconnected.
0
1
Reserved
1
0
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
1
1
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Table 12-8.
Waveform Generation Mode Bit Description
Mode
WGM02
WGM01
WGM00
Timer/Count
er Mode of
Operation
TOP
Update of
OCRx at
TOV Flag
Set on
0
0
0
0
Normal
0xFF
Immediate
MAX
1
0
0
1
PWM, Phase
Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
0
1
1
Fast PWM
0xFF
TOP
MAX
4
1
0
0
Reserved
–
–
–
5
1
0
1
PWM, Phase
Correct
OCRA
TOP
BOTTOM
6
1
1
0
Reserved
–
–
–
7
1
1
1
Fast PWM
OCRA
TOP
TOP
Bit
7
6
5
4
3
2
1
0
FOC0A
FOC0B
–
–
WGM02
CS02
CS01
CS00
TCCR0B
Read/Write
W
W
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0