Table 13-1, Table 13-2, Table 13-3 – Rainbow Electronics ATmega64C1 User Manual
Page 127: Table 13-2 on, Table 13-3 on, Table on, The actual ocnx
127
7647A–AVR–02/08
ATmega32/64/M1/C1
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit correspond-
ing to the OCnA or OCnB pin must be set in order to enable the output driver.
When the OCnA or OCnB is connected to the pin, the function of the COMnx1:0 bits is depen-
dent of the WGMn3:0 bits setting.
shows the COMnx1:0 bit functionality when the
WGMn3:0 bits are set to a Normal or a CTC mode (non-PWM).
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the fast
PWM mode.
Note:
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. In
this case the compare match is ignored, but the set or clear is done at TOP.
for more details.
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase
correct or the phase and frequency correct, PWM mode.
Table 13-1.
Compare Output Mode, non-PWM
COMnA1/COMnB1
COMnA0/COMnB0
Description
0
0
Normal port operation, OCnA/OCnB disconnected.
0
1
Toggle OCnA/OCnB on Compare Match.
1
0
Clear OCnA/OCnB on Compare Match (Set output to
low level).
1
1
Set OCnA/OCnB on Compare Match (Set output to
high level).
Table 13-2.
Compare Output Mode, Fast PWM
COMnA1/COMnB1
COMnA0/COMnB0
Description
0
0
Normal port operation, OCnA/OCnB disconnected.
0
1
WGMn3:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
1
0
Clear OCnA/OCnB on Compare Match, set
OCnA/OCnB at TOP
1
1
Set OCnA/OCnB on Compare Match, clear
OCnA/OCnB at TOP
Table 13-3.
Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM
COMnA1/COMnB1
COMnA0/COMnB0
Description
0
0
Normal port operation, OCnA/OCnB disconnected.