Rainbow Electronics ATmega64C1 - Manual (Page 157)

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7647A–AVR–02/08
ATmega32/64/M1/C1
15. Serial Peripheral Interface – SPI
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega32/64/M1/C1 and peripheral devices or between several AVR devices.
The ATmega32/64/M1/C1 SPI includes the following features:
15.1 Features
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
Figure 15-1. SPI Block Diagram (1)
Note: 1. Refer to Figure 1-1 on page 3 , and Table 9-3 on page 67 for SPI pin placement.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 15-2 . The sys-
tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the
communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and
Slave prepare the data to be sent in their respective shift Registers, and the Master generates
SPI2X
SPI2X
DIVIDER
/2/4/8/16/32/64/128
clk
IO
MISO
MISO
_A
MOSI
MOSI
_A
SCK
SCK
_A
SS
SS_A
SPIPS