Rainbow Electronics ATmega64C1 - Manual (Page 141)

141
7647A–AVR–02/08
ATmega32/64/M1/C1
14.6.1 Value Update Synchronization
New timing values or PSC output configuration can be written during the PSC cycle. Thanks to
LOCK configuration bit, the new whole set of values can be taken into account after the end of
the PSC cycle.
When LOCK configuration bit is set, there is no update. The update of the PSC internal registers
will be done at the end of the PSC cycle if the LOCK bit is released to zero.
The registers which update is synchronized thanks to LOCK are POC, POM2, POCRnSAH/L,
POCRnRAH/L, POCRnSBH/L and POCRnRBH/L.
See these register’s description starting on page 151 .
See “PSC Configuration Register – PCNF” on page 152.
14.7 Overlap Protection
Thanks to Overlap Protection two outputs on a same module cannot be active at the same time.
So it cannot generate cross conduction. This feature can be disactivated thanks to POVEn (PSC
Overlap Enable).