9 can bit timing register 2 - canbt2, 10 can bit timing register 3 - canbt3 – Rainbow Electronics ATmega64C1 User Manual
Page 191
191
7647A–AVR–02/08
ATmega32/64/M1/C1
The period of the CAN controller system clock Tscl is programmable and determines the individ-
ual bit timing.
If ‘BRP[5..0]=0’, see
Section 16.4.3 “Baud Rate” on page 175
.
• Bit 0 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT1 is written.
16.10.9
CAN Bit Timing Register 2 - CANBT2
• Bit 7– Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
• Bit 6:5 – SJW1:0: Re-Synchronization Jump Width
To compensate for phase shifts between clock oscillators of different bus controllers, the control-
ler must re-synchronize on any relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of clock cycles. A bit period may
be shortened or lengthened by a re-synchronization.
• Bit 4 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
• Bit 3:1 – PRS2:0: Propagation Time Segment
This part of the bit time is used to compensate for the physical delay times within the network. It
is twice the sum of the signal propagation time on the bus line, the input comparator delay and
the output driver delay.
• Bit 0 – Reserved Bit
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
16.10.10 CAN Bit Timing Register 3 - CANBT3
Tscl =
BRP[5:0] + 1
clk
IO
frequency
Bit
7
6
5
4
3
2
1
0
-
SJW1
SJW0
-
PRS2
PRS1
PRS0
-
CANBT2
Read/Write
-
R/W
R/W
-
R/W
R/W
R/W
-
Initial Value
-
0
0
-
0
0
0
-
Tsjw = Tscl x (SJW [1:0] +1)
Tprs = Tscl x (PRS [2:0] + 1)
Bit
7
6
5
4
3
2
1
0
-
PHS22
PHS21
PHS20
PHS12
PHS11
PHS10
SMP
CANBT3
Read/Write
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
-
0
0
0
0
0
0
0