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9 serial downloading, 1 serial programming algorithm, Parallel data downloading to the eeprom, see – Rainbow Electronics ATmega64C1 User Manual

Page 305: Serial

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305

7647A–AVR–02/08

ATmega32/64/M1/C1

Notes:

1. t

WLRH

is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits

commands.

2. t

WLRH_CE

is valid for the Chip Erase command.

24.9

Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in

Table 24-14 on page 296

, the pin

mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.

Figure 24-10. Serial Programming and Verify

(1)

Notes:

1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

XTAL1 pin.

2. V

CC

- 0.3V < AVCC < V

CC

+ 0.3V, however, AVCC should always be within 1.8 - 5.5V

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:

Low:> 2 CPU clock cycles for f

ck

< 12 MHz, 3 CPU clock cycles for f

ck

>= 12 MHz

High:> 2 CPU clock cycles for f

ck

< 12 MHz, 3 CPU clock cycles for f

ck

>= 12 MHz

24.9.1

Serial Programming Algorithm

When writing serial data to the ATmega32/64/M1/C1, data is clocked on the rising edge of SCK.

t

BVDV

BS1 Valid to DATA valid

0

250

ns

t

OLDV

OE Low to DATA Valid

250

ns

t

OHDZ

OE High to DATA Tri-stated

250

ns

Table 24-15. Parallel Programming Characteristics, V

CC

= 5V ± 10% (Continued)

Symbol

Parameter

Min

Typ

Max

Units

VCC

GND

XTAL1

SCK_A

MISO_A

MOSI_A

RESET

+1.8 - 5.5V

AVCC

+1.8 - 5.5V

(2)