1 compare output mode and waveform generation – Rainbow Electronics ATmega64C1 User Manual

Page 117

117

7647A–AVR–02/08

ATmega32/64/M1/C1

Secondly the COMnx1:0 bits control the OCnx pin output source.

schematic of the logic affected by the COMnx1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COMnx1:0 bits are shown. When referring to the
OCnx state, the reference is for the internal OCnx Register, not the OCnx pin. If a system reset
occur, the OCnx Register is reset to “0”.

Figure 13-5. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OCnx) from the Waveform
Generator if either of the COMnx1:0 bits are set. However, the OCnx pin direction (input or out-
put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OCnx pin (DDR_OCnx) must be set as output before the OCnx value is visi-
ble on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. Refer to

for

details.

The design of the Output Compare pin logic allows initialization of the OCnx state before the out-
put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of
operation.

See “16-bit Timer/Counter Register Description” on page 126.

The COMnx1:0 bits have no effect on the Input Capture unit.

13.7.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COMnx1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COMnx1:0 = 0 tells the Waveform Generator that no action on the
OCnx Register is to be performed on the next compare match. For compare output actions in the
non-PWM modes refer to

Table 13-1 on page 127

. For fast PWM mode refer to

Table 13-2 on

page 127

, and for phase correct and phase and frequency correct PWM refer to

Table 13-3 on

page 127

PORT

DDR

OCnx

Pin

OCnx