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And ld/or ld, Applicable program areas flags, Function hint – Omron SYSMAC CP CP1E-N@@D@-@ User Manual

Page 49: 2 instructions, And ld, Or ld

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2 Instructions

CP1E CPU Unit Instructions Reference Manual(W483)

Seq

uen

ce Inp

u

t I

n

stru

ctio

ns

2

AND LD/

O

R L

D

AND LD/OR LD

Applicable Program Areas

Flags

There are no flags affected by this instruction.

Function

Hint

Instruction

Mnemonic

Variations

Function

code

Function

AND LOAD

AND LD

---

---

Takes a logical AND between logic blocks.

OR LOAD

OR LD

---

---

Takes a logical OR between logic blocks.

Symbol

AND LD

OR LD

Area

Step program areas

Subroutines

Interrupt tasks

Usage

OK

OK

OK

AND LD

AND LD connects in series the logic block just
before this instruction with another logic block.

The logic block consists of all the instructions
from a LOAD or LOAD NOT instruction until
just before the next LOAD or LOAD NOT
instruction on the same rungs.

OR LD

OR LD connects in parallel the logic block just
before this instruction with another logic block.

The logic block consists of all the instructions
from a LOAD or LOAD NOT instruction until
just before the next LOAD or LOAD NOT
instruction on the same rungs.

AND LD

Three or more logic blocks can be connected in series using this instruction to first connect two of the

logic blocks and then to connect the next and subsequent ones in order. It is also possible to continue
placing this instruction after three or more logic blocks and connect them together in series.

OR LD

Three or more logic blocks can be connected in parallel using this instruction to first connect two of

the logic blocks and then to connect the next and subsequent ones in order. It is also possible to con-
tinue placing this instruction after three or more logic blocks and connect them together in parallel.

Logic block

Logic block

Logic block

Logic block

LD

LD

AND LD

Logic block A

Logic block B

Serial connection between logic block A and
logic block B.

to

to

LD

LD

OR LD

to

to

Logic block A

Logic block B

Parallel connection between logic block A and
logic block B.

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