Rainbow Electronics ATtiny861_V - Manual (Page 51)

51
2588B–AVR–11/06
ATtiny261/461/861
11.1.2 GIMSK – General Interrupt Mask Register
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-
ing edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even
if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is
executed from the INT1 Interrupt Vector.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU
Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-
ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even
if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is
executed from the INT0 Interrupt Vector.
• Bit 5 – PCIE1: Pin Change Interrupt Enable
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt is enabled. Any change on any enabled PCINT7..0 or PCINT15..12 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed
from the PCI Interrupt Vector. PCINT7..0 and PCINT15..12 pins are enabled individually by the
PCMSK0 and PCMSK1 Register.
• Bit 4 – PCIE0: Pin Change Interrupt Enable
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt is enabled. Any change on any enabled PCINT11..8 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt
Vector. PCINT11..8 pins are enabled individually by the PCMSK1 Register.
• Bits 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny261/461/861 and will always read as zero.
11.1.3 GIFR – General Interrupt Flag Register
• Bit 7– INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set
(one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the cor-
responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Bit 7 6 5 4 3 2 1 0
0x3B (0x5B) INT1 INT0 PCIE1 PCIE0 – – – – GIMSK
Read/Write R/W R/W R/W R/w R R R R
Initial Value 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
0x3A (0x5A) INT1 INTF0 PCIF – – – – – GIFR
Read/Write R/W R/W R/W R R R R R
Initial Value 0 0 0 0 0 0 0 0