Rainbow Electronics ATtiny861_V - Manual (Page 109)

109
2588B–AVR–11/06
ATtiny261/461/861
When the Fault Protection mode is enabled by the Fault Protection Enable (FPEN1) bit and a
change of the logic level (an event) occurs on the external interrupt pin (INT0), alternatively on
the Analog Comparator output (ACO), and this change confirms to the setting of the edge detec-
tor, a Fault Protection mode will be triggered. When a Fault Protection is triggered, the COM1x
bits are cleared, Output Comparators are disconnected from the PWM output pins and the
PORTB register bits are connected on the PWM output pins. The Fault Protection Enable
(FPEN1) is automatically cleared at the same system clock as the COM1nx bits are cleared. If
the Fault Protection Interrupt Enable bit (FPIE1) is set, a Fault Protection interrupt is generated
and the FPEN1 bit is cleared. Alternatively the FPEN1 bit can be polled by software to figure out
when the Timer/Counter has entered to Fault Protection mode.
16.9.1 Fault Protection Trigger Source
The main trigger source for the Fault Protection unit is the external interrupt pin (INT0). Alterna-
tively the Analog Comparator output can be used as trigger source for the Fault Protection unit.
The Analog Comparator is selected as trigger source by setting the Fault Protection Analog
Comparator (FPAC1) bit in the Timer/Counter1 Control Register (TCCR1D). Be aware that
changing trigger source can trigger a Fault Protection mode. Therefore it is recommended to
clear the FPF1 flag after changing trigger source, setting edge detector or enabling the Fault
Protection.
Both the external interrupt pin (INT0) and the Analog Comparator output (ACO) inputs are sam-
pled using the same technique as for the T0 pin (
Figure 13-1 on page 69 ). The edge detector is
also identical. However, when the noise canceler is enabled, additional logic is inserted before
the edge detector, which increases the delay by four system clock cycles. An Input Capture can
also be triggered by software by controlling the port of the INT0 pin.
16.9.2 Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Fault Protection Noise Canceler (FPNC1) bit in
Timer/Counter1 Control Register D (TCCR1D). When enabled the noise canceler introduces
additional four system clock cycles of delay from a change applied to the input. The noise can-
celer uses the system clock and is therefore not affected by the prescaler.