Rainbow Electronics ATtiny861_V - Manual (Page 181)

181
2588B–AVR–11/06
ATtiny261/461/861
22.8 Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-
put). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in
Table 22-13 on page 181 , the pin
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
Figure 22-7. Serial Programming and Verify (1)
Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
CLKI pin.
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
>= 12 MHz
High: > 2 CPU clock cycles for f
ck
< 12 MHz, 3 CPU clock cycles for f
ck
>= 12 MHz
Table 22-13. Pin Mapping Serial Programming
Symbol Pins I/O Description
MOSI PB0 I Serial Data in
MISO PB1 O Serial Data out
SCK PB2 I Serial Clock
VCC
GND
SCK
MISO
MOSI
RESET
+1.8 - 5.5V