Rainbow Electronics ATtiny861_V - Manual (Page 50)

50
2588B–AVR–11/06
ATtiny261/461/861
11. External Interrupts
The External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT15..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT15..0 pins are
configured as outputs. This feature provides a way of generating a software interrupt. Pin
change interrupts PCI will trigger if any enabled PCINT15..0 pin toggles. The PCMSK Register
control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT15..0
are detected asynchronously. This implies that these interrupts can be used for waking the part
also from sleep modes other than Idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge or a low level. This is
set up as indicated in the specification for the MCU Control Register – MCUCR. When the INT0
interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the
pin is held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires
the presence of an I/O clock, described in
”Clock Systems and their Distribution” on page 24 .
Low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be
used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in
all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-
rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in
”System Clock and Clock Options” on page 24 .
11.1 Register Description
11.1.1 MCUCR – MCU Control Register
The MCU Register contains control bits for interrupt sense control.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 or INT1 if the SREG I-flag and the
corresponding interrupt mask are set. The level and edges on the external INT0 or INT1 pin that
activate the interrupt are defined in
Table 11-1 . The value on the INT0 or INT1 pin is sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt.
Bit 7 6 5 4 3 2 1 0
0x35 (0x55) – PUD SE SM1 SM0 – ISC01 ISC00 MCUCR
Read/Write R R/W R/W R/W R/W R R/W R/W
Initial Value 0 0 0 0 0 0 0 0
Table 11-1. Interrupt 0 Sense Control
ISC01 ISC00 Description
0 0 The low level of INT0 or INT1 generates an interrupt request.
0 1 Any logical change on INT0 or INT1 generates an interrupt request.
1 0 The falling edge of INT0 or INT1 generates an interrupt request.
1 1 The rising edge of INT0 or INT1 generates an interrupt request.