Rainbow Electronics ATtiny861_V - Manual (Page 133)

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2588B–AVR–11/06
ATtiny261/461/861
17.4 Alternative USI Usage
When the USI unit is not used for serial communication, it can be set up to do alternative tasks
due to its flexible design.
17.4.1 Half-duplex Asynchronous Data Transfer
By utilizing the USI Data Register in Three-wire mode, it is possible to implement a more com-
pact and higher performance UART than by software only.
17.4.2 4-bit Counter
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will generate an increment.
17.4.3 12-bit Timer/Counter
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
17.4.4 Edge Triggered External Interrupt
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature
is selected by the USICS1 bit.
17.4.5 Software Interrupt
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
17.5 Register Descriptions
17.5.1 USIDR – USI Data Register
When accessing the USI Data Register (USIDR) the Serial Register can be accessed directly. If
a serial clock occurs at the same cycle the register is written, the register will contain the value
written and no shift is performed. A (left) shift operation is performed depending of the
USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a
Timer/Counter0 Compare Match, or directly by software using the USICLK strobe bit. Note that
even when no wire mode is selected (USIWM1..0 = 0) both the external data input (DI/SDA) and
the external clock input (USCK/SCL) can still be used by the USI Data Register.
The output pin in use, DO or SDA depending on the wire mode, is connected via the output latch
to the most significant bit (bit 7) of the Data Register. The output latch is open (transparent) dur-
ing the first half of a serial clock cycle when an external clock source is selected (USICS1 = 1),
and constantly open when an internal clock source is used (USICS1 = 0). The output will be
changed immediately when a new MSB written as long as the latch is open. The latch ensures
that data input is sampled and data output is changed on opposite clock edges.
Note that the corresponding Data Direction Register to the pin must be set to one for enabling
data output from the USI Data Register.
Bit 7 6 5 4 3 2 1 0
0x0F (0x2F) MSB LSB USIDR
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Initial Value 0 0 0 0 0 0 0 0