Power management and sleep modes, 1 sleep modes, 2 idle mode – Rainbow Electronics ATtiny861_V User Manual
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2588B–AVR–11/06
ATtiny261/461/861
8.
Power Management and Sleep Modes
The high performance and industry leading code efficiency makes the AVR microcontrollers an
ideal choise for low power applications.
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
8.1
Sleep Modes
Figure 7-1 on page 24
presents the different clock systems in the ATtiny261/461/861, and their
distribution. The figure is helpful in selecting an appropriate sleep mode.
shows the
different sleep modes and their wake up sources.
Note:
1. For INT0 and INT1, only level interrupt.
To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a
SLEEP instruction must be executed. The SM1..0 bits in the MCUCR Register select which
sleep mode (Idle, ADC Noise Reduction, Power-down, or Standby) will be activated by the
SLEEP instruction. See
Table 8-2
for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
8.2
Idle Mode
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the
interrupt system to continue operating. This sleep mode basically halts clk
CPU
and clk
FLASH
, while
allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,
the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator
Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the
ADC is enabled, a conversion starts automatically when this mode is entered.
Table 8-1.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains
Oscillators
Wake-up Sources
Sleep Mode
clk
CPU
clk
FL
A
S
H
clk
IO
clk
ADC
clk
PCK
Main
Cl
oc
k
Sour
ce Enab
led
INT
0
, INT
1
and
Pin Ch
ange
SPM/EEPR
OM
Rea
d
y
ADC
WD
T
USI
Ot
her I/O
Idle
X
X
X
X
X
X
X
X
X
X
ADC Noise
Reduction
X
X
X
(1)
X
X
X
X
Power-down
X
(1)
X
X
Standby
X
(1)
X
X