3 adcl and adch - the adc data register, 1 adlar = 0, 2 adlar = 1 – Rainbow Electronics ATtiny861_V User Manual
Page 158: 4 adcsrb - adc control and status register b, Table 19-5. adc prescaler selections (continued)
158
2588B–AVR–11/06
ATtiny261/461/861
19.10.3
ADCL and ADCH – The ADC Data Register
19.10.3.1
ADLAR = 0
19.10.3.2
ADLAR = 1
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in
.
19.10.4
ADCSRB – ADC Control and Status Register B
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
Table 19-5.
ADC Prescaler Selections (Continued)
ADPS2
ADPS1
ADPS0
Division Factor
Bit
15
14
13
12
11
10
9
8
0x05 (0x25)
–
–
–
–
–
–
ADC9
ADC8
ADCH
0x04 (0x24)
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
7
6
5
4
3
2
1
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15
14
13
12
11
10
9
8
0x05 (0x25)
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
0x04 (0x24)
ADC1
ADC0
–
–
–
–
–
–
ADCL
7
6
5
4
3
2
1
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
7
6
5
4
3
2
1
0
0x03 (0x23)
BIN
GSEL
-
REFS2
MUX5
ADTS2
ADTS1
ADTS0
ADCSRB
Read/Write
R/W
R/W
R/W
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0