Rainbow Electronics W90N745CDG User Manual

Page 92

W90N745CD/W90N745CDG

Publication Release Date: September 22, 2006

Revision

Continued.

BITS

DESCRIPTION

[3]

FLHS

Flush I-Cache/D-Cache single line
Flushes the entire I-Cache/D-Cache per line. Both WAY and ADDR
bits in CAHADR register must be specified.

[2] FLHA

Flush I-Cache/D-Cache entirely
To flush the entire I-Cache/D-Cache, also flushes any locked-down
code. If the I-Cache/D-Cache contains locked down code, the
programmer must flush lines individually

[1] DCAH

D-Cache selected
When set to “1”, the command set is executed with D-Cache.

[0] ICAH

I-Cache selected
When set to “1”, the command set is executed with I-Cache.

NOTE：When using the FLHA or ULKA command, you can set both ICAH and DCAH bits to execute
entire I-Cache and D-Cache flushing or unlocking. But, FLHS and ULKS commands can only be
executed with a cache line specified by CAHADR register in I-Cache or D-Cache at a time. If you set
both ICAH and DCAH bits, and set FLHS or ULKS command bit, it will be treated as an invalid
command and no operation is done and the command terminates with no exception.

The Drain Write Buffer operation is only for D-Cache. To perform this operation, you must set DRWB
and DCAH bits. If the ICAH bit is set when using DRWB command, it will be an invalid command and no
operation is done and the command terminates with no exception.