Rainbow Electronics W90N745CDG - Manual (Page 39)

W90N745CD/W90N745CDG
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Table 6.2.9 and Table 6.2.10
Using little-endian and word access, Program/Data path between register and external memory
WA = Address whose LSB is 0,4,8,C X = Don’t care
nWBE [1-0] / SDQM [1-0] = A means active and U means inactive
Table 6.2.9 Word access write operation with little Endian
ACCESS OPERATION WRITE OPERATION (CPU REGISTER Î EXTERNAL MEMORY)
XD WIDTH HALF WORD BYTE
Bit Number
CPU Reg Data
31 0
ABCD 31 0
ABCD
SA WA WA
Bit Number
SD
31 0
AB CD 31 0
A B C D
Bit Number
ED
15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
XA WA WA+2 WA WA+1 WA+2 WA+3
nWBE [1-0] /
SDQM [1-0]
AA AA XA XA XA XA
Bit Number
XD
15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
Bit Number
Ext. Mem Data
15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
Timing Sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write
Table 6.2.10 Word access read operation with Little Endian
ACCESS OPERATION READ OPERATION (CPU REGISTER Í EXTERNAL MEMORY)
XD Width Half Word Byte
Bit Number
CPU Reg Data
31 0
ABCD 31 0
ABCD
SA WA WA
Bit Number
SD
31 0
AB CD 31 0
A B C D
Bit Number
ED
31 0
XX CD 31 0
AB CD 31 0
X X X D
31 0
X X C D
31 0
X B C D
31 0
A B C D
XA WA WA+2 WA WA+1 WA+2 WA+3
SDQM [1-0] AA AA XA XA XA XA
Bit Number
XD
15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
Bit Number
Ext. Mem Data
15 0
CD
15 0
AB
7 0
D
7 0
C
7 0
B
7 0
A
Timing Sequence 1st write 2nd write 1st write 2nd write 3rd write 4th write