Rainbow Electronics W90N745CDG - Manual (Page 303)

W90N745CD/W90N745CDG
Publication Release Date: September 22, 2006
- 299 - Revision A2
AIC Functional Description
Hardware Interrupt Vectoring
The hardware interrupt vectoring can be used to shorten the interrupt latency. If not used, priority
determination must be carried out by software. When the Interrupt Priority Encoding Register
(AIC_IPER) is read, it will return an integer representing the channel that is active and having the
highest priority. This integer is equivalent to multiplied by 4 (shifted left two bits to word-align it) such
that it may be used directly to index into a branch table to select the appropriate interrupt service
routine vector.
Priority Controller
An 8-level priority encoder controls the nIRQ line. Each interrupt source belongs to priority group
between of 0 to 7. Group 0 has the highest priority and group 7 the lowest. When more than one
unmasked interrupt channels are active at a time, the interrupt with the highest priority is serviced first.
If all active interrupts have equal priority, the interrupt with the lowest interrupt source number is
serviced first.
The current priority level is defined as the priority level of the interrupt with the highest priority at the
time the register AIC_IPER is read. In the case when a higher priority unmasked interrupt occurs while
an interrupt already exits, there are two possible outcomes depending on whether the AIC_IPER has
been read.
If the processor has already read the AIC_IPER and caused the nIRQ line to be de-asserted, then the
nIRQ line is reasserted. When the processor has enabled nested interrupts and reads the AIC_IPER
again, it reads the new, higher priority interrupt vector. At the same time, the current priority level is
updated to the higher priority.
If the AIC_IPER has not been read after the nIRQ line has been asserted, then the processor will read
the new higher priority interrupt vector in the AIC_IPER register and the current priority level is
updated.
When the End of Service Command Register (AIC_EOSCR) is written, the current interrupt level is
updated with the last stored interrupt level from the stack (if any). Therefore, at the end of a higher
priority interrupt, the AIC returns to the previous state corresponding to the preceding lower priority
interrupt which had been interrupted.
Interrupt Handling
When the IRQ line is asserted, the interrupt handler must read the AIC_IPER as soon as possible.
This can de-assert the nIRQ request to the processor and clears the interrupt if it is programmed to be
edge triggered. This allows the AIC to assert the nIRQ line again when a higher priority unmasked
interrupt occurs.
The AIC_EOSCR (End of Service Command Register) must be written at the end of the interrupt
service routine. This permits pending interrupts to be serviced.