Rainbow Electronics W90N745CDG - Manual (Page 267)

W90N745CD/W90N745CDG
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y Line break generation and detection
y False start bit detection
y Full prioritized interrupt system controls
y Loop back mode for internal diagnostic testing
6.10.5.1. UART Control Registers Map
R: read only, W: write only, R/W: both read and write, C: Only value 0 can be written
REGISTER OFFSET R/W DESCRIPTION RESET VALUE
UART_RBR 0x00 R Receive Buffer Register (DLAB = 0) Undefined
UART_THR 0x00 W Transmit Holding Register (DLAB = 0) Undefined
UART_IER 0x04 R/W Interrupt Enable Register (DLAB = 0) 0x0000_0000
UART_DLL 0x00 R/W
Divisor Latch Register (LS)
(DLAB = 1)
0x0000_0000
UART_DLM 0x04 R/W
Divisor Latch Register (MS)
(DLAB = 1)
0x0000_0000
UART_IIR 0x08 R Interrupt Identification Register 0x8181_8181
UART_FCR 0x08 W FIFO Control Register Undefined
UART_LCR 0x0C R/W Line Control Register 0x0000_0000
UART_MCR 0x10 R/W Modem Control Register (Optional) 0x0000_0000
UART_LSR 0x14 R Line Status Register 0x6060_6060
UART_MSR 0x18 R MODEM Status Register (Optional) 0x0000_0000
UART_TOR 0x1C R/W Time Out Register 0x0000_0000
Note: Real register address = 0xFFF8_0000+ (UART number – 1) * (0x0100) + offset
Note: All of these registers are implemented 8-bit in UART design and it will be repeated 4 times
before send to APB bus. For example, when ARM CPU read register UARTn_BRR, ARM CPU will get
UART0_RBR = {RBR[7:0], RBR[7:0], RBR[7:0], RBR[7:0]}.
UART Receive Buffer Register (UART_RBR)
REGISTER OFFSET R/W DESCRIPTION RESET VALUE
UART_RBR 0x00 R Receive Buffer Register (DLAB = 0) Undefined