Rainbow Electronics W90N745CDG - Manual (Page 134)

W90N745CD/W90N745CDG
Publication Release Date: September 22, 2006
- 129 - Revision A2
Maximum Receive Frame Control Register (DMARFC)
The DMARFC defines the maximum frame length for a received frame that can be stored in the
system memory. It is recommend that only use this register while S/W wants to receive a frame which
length is greater than 1518 bytes.
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
DMARFC 0xFFF0_30A8 R/W
Maximum Receive Frame Control
Register
0x0000_0800
31 30 29 28 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
RXMS
7 6 5 4 3 2 1 0
RXMS
BITS DESCRIPTIONS
[31:16] Reserved -
[15:0] RXMS
The Maximum Receive Frame Length defines the
maximum frame length for received frame. If the frame
length of received frame is greater than RXMS, and bit
EnDFO of MIEN register is also enabled, the bit DFOI of
MISTA register is set and the Rx interrupt is triggered.
It is recommended that only use RXMS to qualify the length
of received frame while S/W wants to receive a frame which
length is greater than 1518 bytes.