Rainbow Electronics W90N745CDG - Manual (Page 56)

W90N745CD/W90N745CDG
Publication Release Date: September 22, 2006
- 51 - Revision A2
I²S Clock Control Register (I²SCKCON)
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
I²SCKCON 0xFFF0_0014 R/W I²S PLL clock Control Register 0x0000_0000
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED I
²
SPLLEN
7 6 5 4 3 2 1 0
PRESCALE
BITS DESCRIPTION
[31:9] RESERVED -
[8] I²SPLLEN
I²S PLL clock source enable
Set this bit will enable PLL1 clock output to audio I²S clock input.
1 = Enable PLL1 clock source for audio I²S
0 = Disable PLL1 clock source for audio I²S
[7:0] PRESCALE
The PLL1 is used by I²S, if in use, software can using this
prescaler to generate an appropriate clock nearly 12.288M or
16.934M. The clock is generated as below, and if PRESCALE =0,
the PLL_AUDIO is the same frequency as FOUT “PLL_AUDIO =
PLL_FOUT/(PRESCALE +1)”