Rainbow Electronics W90N745CDG - Manual (Page 141)

W90N745CD/W90N745CDG
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MAC Interrupt Status Register (MISTA)
The MISTA keeps much EMC statuses, like frame transmission and reception status, internal FIFO
status and also NATA processing status. The statuses kept in MISTA will trigger the reception or
transmission interrupt. The MISTA is a write clear register and write 1 to corresponding bit clears the
status and also clears the interrupt.
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
MISTA 0xFFF0_30B0 R/W MAC Interrupt Status Register 0x0000_0000
31 30 29 28 27 26 25 24
Reserved TxBErr
23 22 21 20 19 18 17 16
TDU LC TXABT NCS EXDEF TXCP TXEMP TXINTR
15 14 13 12 11 10 9 8
Reserved CFR Reserved RxBErr RDU DENI DFOI
7 6 5 4 3 2 1 0
MMP RP ALIE RXGD PTLE RXOV CRCE RXINTR
BITS DESCRIPTIONS
[31:25] Reserved -
[24] TxBErr
The Transmit Bus Error Interrupt high indicates the memory
controller replies ERROR response while EMC access system
memory through TxDMA during packet transmission process. Reset
EMC is recommended while TxBErr status is high.
If the TxBErr is high and EnTxBErr of MIEN register is enabled, the
TxINTR will be high. Write 1 to this bit clears the TxBErr status.
1’b0: No ERROR response is received.
1’b1: ERROR response is received.
[23] TDU
The Transmit Descriptor Unavailable Interrupt high indicates that
there is no available Tx descriptor for packet transmission and
TxDMA will stay at Halt state. Once, the TxDMA enters the Halt
state, S/W must issues a write command to TSDR register to make
TxDMA leave Halt state while new Tx descriptor is available.
If the TDU is high and EnTDU of MIEN register is enabled, the
TxINTR will be high. Write 1 to this bit clears the TDU status.
1’b0: Tx descriptor is available.
1’b1: Tx descriptor is unavailable.