Rainbow Electronics W90N745CDG - Manual (Page 354)

W90N745CD/W90N745CDG
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6.15.1 USI Timing Diagram
The timing diagram of USI is shown as following.
MSB
(Tx[7])
LSB
(Tx[0])
MSB
(Rx[7])
LSB
(Rx[0])
mw_ss_o
mw_sclk_o
mw_so_o
mw_si_i
CNTRL[LSB]=0, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08,
CNTRL[Tx_NEG]=1, CNTRL[Rx_NEG]=0, SSR[SS_LVL]=0
Tx[6] Tx[5] Tx[4] Tx[3] Tx[2] Tx[1]
Rx[6] Rx[5] Rx[4] Rx[3] Rx[2] Rx[1]
Figure 6.15.1 USI Timing
mw_ss_o
mw_sclk_o
mw_so_o
mw_si_i
CNTRL[LSB]=1, CNTRL[Tx_NUM]=0x0, CNTRL[Tx_BIT_LEN]=0x08,
CNTRL[Tx_NEG]=0, CNTRL[Rx_NEG]=1, SSR[SS_LVL]=0
MSB
(Tx[7])
LSB
(Tx[0])
MSB
(Rx[7])
LSB
(Rx[0])
Tx[1] Tx[2] Tx[3] Tx[4] Tx[5] Tx[6]
Rx[1] Rx[2] Rx[3] Rx[4] Rx[5] Rx[6]
Figure 6.15.2 Alternate Phase SCLK Clock Timing