Rainbow Electronics W90N745CDG - Manual (Page 7)

W90N745CD/W90N745CDG
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2. FEATURES
Architecture
• Fully 16/32-bit RISC architecture
• Little/Big-Endian mode supported
• Efficient and powerful ARM7TDMI core
• Cost-effective JTAG-based debug solution
External Bus Interface
• 8/16-bit external bus support for ROM/SRAM, flash memory, SDRAM and external I/Os
• Support for SDRAM
• Programmable access cycle (0-7 wait cycle)
• Four-word depth write buffer for SDRAM write data
• Cost-effective memory-to-peripheral DMA interface
Instruction and Data Cache
• Two-way, set-associative, 4K-byte I-cache and 4K-byte D-cache
• Support for LRU (Least Recently Used) protocol
• Cache can be configured as internal SRAM
• Support cache lock function
Ethernet MAC Controller
• DMA engine with burst mode
• MAC Tx/Rx buffers (256 bytes Tx, 256 bytes Rx)
• Data alignment logic
• Endian
translation
• 100/10 Mbit per second operation
• Full compliance with IEEE standard 802.3
• RMII interface only
• Station Management Signaling
• On-chip CAM (up to 16 destination addresses)
• Full-duplex mode with PAUSE feature
• Long/short packet modes
• PAD
generation