Rainbow Electronics W90N745CDG User Manual
Page 91
W90N745CD/W90N745CDG
- 86 -
Control Register (CAHCON)
Cache controller supports one Control register used to control the following operations.
y
Flush I-Cache and D-Cache
y
Load and lock I-Cache and D-Cache
y
Unlock I-Cache and D-Cache
y
Drain write buffer
These command set bits in CAHCON register are auto-clear bits. As the end of execution, that command
set bit will be cleared to “0” automatically.
REGISTER ADDRESS R/W
DESCRIPTION
RESET
VALUE
CAHCON
0xFFF0_2004
R/W Cache control register
0x0000_0000
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
7
6
5
4
3
2
1
0
DRWB ULKS ULKA LDLK FLHS FLHA DCAH ICAH
BITS
DESCRIPTION
[31:8] RESERVED
-
[7] DRWB
Drain write buffer
Forces write buffer data to be written to main memory.
[6] ULKS
Unlock I-Cache/D-Cache single line
Unlocks the I-Cache/D-Cache per line. Both WAY and ADDR bits in
CAHADR register must be specified.
[5] ULKA
Unlock I-Cache/D-Cache entirely
Unlocks the entire I-Cache/D-Cache, the lock bit “L” will be cleared
to 0.
[4] LDLK
Load and Lock I-Cache/D-Cache
Loads the instruction or data from external memory and locks into
cache. Both WAY and ADDR bits in CAHADR register must be
specified.