Rainbow Electronics W90N745CDG - Manual (Page 42)

W90N745CD/W90N745CDG
Publication Release Date: September 22, 2006
- 37 - Revision A2
6.2.5 Bus Arbitration
The W90N745’s internal function blocks or external devices can request mastership of the system bus
and then hold the system bus in order to perform data transfers. Because the design of W90N745 bus
allows only one bus master at a time, a bus controller is required to arbitrate when two or more internal
units or external devices simultaneously request bus mastership. When bus mastership is granted to an
internal function block or an external device, other pending requests are not acknowledged until the
previous bus master has released the bus.
W90N745 supports two priority modes, the Fixed Priority Mode and the Rotate Priority Mode,
depends on the ARBCON register PRTMOD bit setting.
6.2.5.1. Fixed Priority Mode
In Fixed Priority Mode (PRTMOD=0, default value), to facilitate bus arbitration, priorities are assigned to
each internal W90N745 function block. The bus controller arbitration requests for the bus mastership
according to these fixed priorities. In the event of contention, mastership is granted to the function block
with the highest assigned priority. These priorities are listed in Table 6.2.15.
W90N745 allows raising ARM Core priority to second if an unmasked interrupt occurred. If IPEN bit, Bit 1
of the Arbitration Control Register (ARBCON), is set to “0”, the priority of ARM Core is fixed to lowest.
If IPEN bit is set to “1” and if no unmasked interrupt request, then the ARM Core’s priority is still lowest
and the IPACT=0, Bit 2 of the Arbitration Control Register (ARBCON) ； If there is an unmasked
interrupt request, then the ARM Core’s priority is raised to first and IPACT=1.
If IPEN is set, an interrupt handler will normally clear IPACT at the end of the interrupt routine to allow an
alternate bus master to regain the bus; however, if IPEN is cleared, no additional action need be taken in
the interrupt handler. The IPACT bit can be read and written. Writing with “0”, the IPACT bit is cleared,
but it will be no effect as writing with “1”.
Table 6.2.15 Bus Priorities for Arbitration in Fixed Priority Mode
BUS FUNCTION BLOCK
PRIORITY IPACT = 0 IPEN = 1 AND IPACT = 1
1 (Highest) Audio Controller (AC97 & I²S) ARM Core
2 General DMA0 Audio Controller (AC97 & I²S)
3 General DMA1 General DMA0
4 EMC DMA General DMA1
5 USB Host EMC DMA
6 USB Device USB Host
7(Lowest) ARM Core USB Device