Rainbow Electronics W90N745CDG - Manual (Page 74)

W90N745CD/W90N745CDG
Publication Release Date: September 22, 2006
- 69 - Revision A2
Timing Control Registers （SDTIME0/1）
W90N745 offers the flexible timing control registers to control the generation and processing of the
control signals and can achieve you use different speed of SDRAM
REGISTER ADDRESS R/W DESCRIPTION RESET VALUE
SDTIME0 0xFFF0_1010 R/W SDRAM bank 0 timing control register 0x0000_0000
SDTIME1 0xFFF0_1014 R/W SDRAM bank 1 timing control register 0x0000_0000
31 30 29 28 27 26 25 24
RESERVED
23 22 21 20 19 18 17 16
RESERVED
15 14 13 12 11 10 9 8
RESERVED tRCD
7 6 5 4 3 2 1 0
tRDL tRP tRAS
BITS DESCRIPTION
[31:11] RESERVED -
[10:8] tRCD
SDRAM bank 0/1, /RAS to /CAS delay
tRCD [10:8] MCLK
0 0 0 1
0 0 1 2
0 1 0 3
0 1 1 4
1 0 0 5
1 0 1 6
1 1 0 7
1 1 1 8
[7:6] tRDL
SDRAM bank 0/1, Last data in to pre-charge command
tRDL [7:6] MCLK
0 0 1
0 1 2
1 0 3
1 1 4