Rainbow Electronics W90N745CDG User Manual
Page 387
W90N745CD/W90N745CDG
Publication Release Date: September 22, 2006
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383
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Revision
A2
PS2 Host Controller Status Register (PS2_STS)
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
PS2STS 0xFFF8_9004
R/W
Status
register
0x0000_0000
31
30
29
28
27
26
25
24
RESERVED
23
22
21
20
19
18
17
16
RESERVED
15
14
13
12
11
10
9
8
RESERVED
7
6
5
4
3
2
1
0
RESERVED TX_err
TX_IRQ
RESERVED
RX_IRQ
BITS
DESCRIPTIONS
[31:6] RESERVED
-
[5]
TX_err
This Transmit Error Status bit indicates software that device
doesn’t response ACK after Host wrote a command to it.
This bit is valid when TX_IRQ is asserted. It will automatically
reset after software starts next command writing process.
This bit is read only.
[4]
TX_IRQ
This Transmit Complete Interrupt bit indicates software that
the process of Host controller writing command to device is
finished. Software needs to write one to this bit to clear this
interrupt.
[3:1]
Reserved
[0]
RX_IRQ
This Receive Interrupt bit indicates software that Host
controller receives one byte data from device. This data is
stored at PS2_SCANCODE register. Software needs to write
one to this bit to clear this interrupt after reading receiving
data in RX_SCAN_CODE register. Note that the reception of
the Extend (0xE0) and Release (0xF0) scan code will not
cause an interrupt by host. The case of the shift key codes
will be determined by the TRAP_SHIFT bit of PS2_CMD
register.