Rainbow Electronics W90N745CDG User Manual
Page 135
W90N745CD/W90N745CDG
- 130 -
MAC Interrupt Enable Register (MIEN)
The MIEN controls the enable of EMC interrupt status to generate interrupt. Two interrupts, RXINTR
for frame reception and TXINTR for frame transmission, are generated from EMC to CPU.
REGISTER
ADDRESS
R/W
DESCRIPTION
RESET VALUE
MIEN
0xFFF0_30AC R/W
MAC Interrupt Enable Register
0x0000_0000
31
30
29
28
27
26
25
24
Reserved EnTxBErr
23
22
21
20
19
18
17
16
EnTDU EnLC
EnTXABT
EnNCS
EnEXDEF
EnTXCP
EnTXEMP
EnTXINTR
15
14
13
12
11
10
9
8
Reserved EnCFR
Reserved
EnRxBErr
EnRDU EnDEN
EnDFO
7
6
5
4
3
2
1
0
EnMMP EnRP EnALIE EnRXGD
EnPTLE
EnRXOV
EnCRCE
EnRXINTR
BITS
DESCRIPTIONS
[31:25] Reserved
-
[24] EnTxBErr
The Enable Transmit Bus Error Interrupt controls the TxBErr
interrupt generation. If TxBErr of MISTA register is set, and both
EnTxBErr and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTxBErr or EnTXINTR is disabled, no Tx interrupt
is generated to CPU even the TxBErr of MISTA register is set.
1’b0: TxBErr of MISTA register is masked from Tx interrupt generation.
1’b1: TxBErr of MISTA register can participate in Tx interrupt
generation.
[23] EnTDU
The Enable Transmit Descriptor Unavailable Interrupt controls the
TDU interrupt generation. If TDU of MISTA register is set, and both
EnTDU and EnTXINTR are enabled, the EMC generates the Tx
interrupt to CPU. If EnTDU or EnTXINTR is disabled, no Tx interrupt is
generated to CPU even the TDU of MISTA register is set.
1’b0: TDU of MISTA register is masked from Tx interrupt generation.
1’b1: TDU of MISTA register can participate in Tx interrupt generation.