Artesyn MVME2502 Installation and Use (April 2015) - Manual (Page 93)

Functional Description
MVME2502 Installation and Use (6806800R96E) 93
4.4.2 P2020 Internal Timer
The processor's internal timer is composed of eight global timers divided into two groups of
four timers each. Each timer has four individual configuration registers and they cannot be
cascaded together.
4.4.3 Watchdog Timer
The on-board CPLD provides programmable 16-bit watchdog timers. It has a 1 ms resolution
and generates a board reset when the counter expires. Interrupt is generated to the processor
when this occurs. Default value is 60 seconds.
4.4.4 CPLD Tick Timer
The MVME2502 supports three independent 32-bit timers that are implemented on the CPLD
to provide fully programmable registers for the timers.
4.5 Ethernet Interfaces
The MVME2502 has three eTSEC controllers. Each one supports RGMII, GMII, and SGMII
interface to the external PHY. All controllers can only be utilized when using the RGMII
interface. Using the GMII allows only up to two usable controllers.
MVME2502 provides two 10/100/1000 Ethernet interfaces on the front panel and another two
are routed to the RTM through the backplane connector. Due to controller limitations, one
controller is designed to be routed to the front panel or to the RTM. This setting is possible by
using a third party gigabit Ethernet LAN switch with a single enable switch such as PERICOM’s
P13L301D. The routing direction is configured through the on-board dip switch.
The registers of the PHY are accessed through the processor’s two-wire Ethernet management
interface.The front panel RJ45 connector has integrated speed and activity status indicator
LEDs. Isolation transformers are provided on the board for each port.