Artesyn MVME2500 Installation and Use (April 2015) Instruction Manuals and User Guides
We have 2 Instruction Manuals and User Guides for MVME2500 Installation and Use (April 2015) Artesyn
Manuals 
| Recognized languages: | English |
|---|---|
| Pages: | 150 |
| Size: | 9.12 MB |
Show table of contents
Document Outline
- MVME2500-ECC
- Contents
- About this Manual
- Introduction
- Hardware Preparation and Installation
- Controls, LEDs, and Connectors
- Functional Description
- 4.1 Block Diagram
- 4.2 Chipset
- 4.2.1 e500 Processor Core
- 4.2.2 Integrated Memory Controller
- 4.2.3 PCI Express Interface
- 4.2.4 Local Bus Controller (LBC)
- 4.2.5 Secure Digital Hub Controller (SDHC)
- 4.2.6 I2C Interface
- 4.2.7 USB Interface
- 4.2.8 DUART
- 4.2.9 DMA Controller
- 4.2.10 Enhanced Three-Speed Ethernet Controller (eTSEC)
- 4.2.11 General Purpose I/O (GPIO)
- 4.2.12 Security Engine (SEC) 3.1
- 4.2.13 Common On-Chip Processor (COP)
- 4.2.14 P20x0 Hardware Configuration Pins
- 4.3 System Memory
- 4.4 Timers
- 4.5 Ethernet Interfaces
- 4.6 SPI Bus Interface
- 4.7 Front UART Control
- 4.8 Rear UART Control
- 4.9 PMC/XMC Sites
- 4.10 SATA Interface
- 4.11 VME Support
- 4.12 USB
- 4.13 I2C Devices
- 4.14 Reset/Control FPGA
- 4.15 Power Management
- 4.16 Clock Structure
- 4.17 Reset Structure
- 4.18 Thermal Management
- 4.19 Real-Time Clock Battery
- 4.20 Debugging Support
- 4.21 Rear Transition Module (RTM)
- Memory Maps and Registers
- 5.1 Overview
- 5.2 Memory Map
- 5.3 Linux Devices Memory Map
- 5.4 Programmable Logic Device (PLD) Registers
- 5.4.1 PLD Revision Register
- 5.4.2 PLD Year Register
- 5.4.3 PLD Month Register
- 5.4.4 PLD Day Register
- 5.4.5 PLD Sequence Register
- 5.4.6 PLD Power Good Monitor Register
- 5.4.7 PLD LED Control Register
- 5.4.8 PLD PCI/PMC/XMC Monitor Register
- 5.4.9 PLD U-Boot and TSI Monitor Register
- 5.4.10 PLD Boot Bank Register
- 5.4.11 PLD Write Protect and I2C Debug Register
- 5.4.12 PLD Test Register 1
- 5.4.13 PLD Test Register 2
- 5.4.14 PLD GPIO2 Interrupt Register
- 5.4.15 Reset Control and Reset Reason Register
- 5.4.16 PLD Watchdog Timer Refresh Register
- 5.4.17 PLD Watchdog Control Register
- 5.4.18 PLD Watchdog Timer Count Register
- 5.5 External Timer Registers
- Boot System
- Programming Model
- A Replacing the Battery
- B Related Documentation
- Safety Notes
- Sicherheitshinweise
| Recognized languages: | English |
|---|---|
| Pages: | 166 |
| Size: | 10.04 MB |
Show table of contents
Document Outline
- MVME2502
- Contents
- About this Manual
- Safety Notes
- Sicherheitshinweise
- Introduction
- Hardware Preparation and Installation
- Controls, LEDs, and Connectors
- Functional Description
- 4.1 Block Diagram
- 4.2 Chipset
- 4.2.1 e500 Processor Core
- 4.2.2 Integrated Memory Controller
- 4.2.3 PCI Express Interface
- 4.2.4 Local Bus Controller (LBC)
- 4.2.5 Secure Digital Host Controller (SDHC)
- 4.2.6 I2C Interface
- 4.2.7 USB Interface
- 4.2.8 DUART
- 4.2.9 DMA Controller
- 4.2.10 Enhanced Three-Speed Ethernet Controller (eTSEC)
- 4.2.11 General Purpose I/O (GPIO)
- 4.2.12 Security Engine (SEC) 3.1
- 4.2.13 Common On-Chip Processor (COP)
- 4.2.14 P2020 Strapping Pins
- 4.3 System Memory
- 4.4 Timers
- 4.5 Ethernet Interfaces
- 4.6 SPI Bus Interface
- 4.7 Front UART Control
- 4.8 Rear UART Control
- 4.9 PMC/XMC Sites
- 4.10 SATA Interface
- 4.11 VME Support
- 4.12 USB
- 4.13 I2C Devices
- 4.14 Reset/Control CPLD
- 4.15 Power Management
- 4.16 Clock Structure
- 4.17 Reset Structure
- 4.18 Thermal Management
- 4.19 Real-Time Clock Battery
- 4.20 Debugging Support
- 4.21 Rear Transition Module (RTM)
- Memory Maps and Registers
- 5.1 Overview
- 5.2 Memory Map
- 5.3 Flash Memory Map
- 5.4 Linux Devices Memory Map
- 5.5 Programmable Logic Device (PLD) Registers
- 5.5.1 PLD Revision Register
- 5.5.2 PLD Year Register
- 5.5.3 PLD Month Register
- 5.5.4 PLD Day Register
- 5.5.5 PLD Sequence Register
- 5.5.6 PLD Power Good Monitor Register
- 5.5.7 PLD LED Control Register
- 5.5.8 PLD PCI/PMC/XMC (Slot1) Monitor Register
- 5.5.9 PLD PCI/PMC/XMC (Slot2) Monitor Register
- 5.5.10 PLD U-Boot and TSI Monitor Register
- 5.5.11 PLD Boot Bank Register
- 5.5.12 PLD Write Protect and I2C Debug Register
- 5.5.13 PLD Test Register 1
- 5.5.14 PLD Test Register 2
- 5.5.15 PLD GPIO2 Interrupt Register
- 5.5.16 PLD Shutdown and Reset Control and Reset Reason Register
- 5.5.17 EMMC Reset Register
- 5.5.18 PLD Watchdog Timer Refresh Register
- 5.5.19 PLD Watchdog Control Register
- 5.5.20 PLD Watchdog Timer Count Register
- 5.5.21 PLD Watchdog Timer Count Value Register
- 5.6 External Timer Registers
- Boot System
- Programming Model
- A Replacing the Battery
- B Related Documentation