Artesyn MVME2502 Installation and Use (April 2015) - Manual (Page 85)

Functional Description
MVME2502 Installation and Use (6806800R96E) 85
4.2.2 Integrated Memory Controller
A fully programmable DDR SDRAM controller supports most JEDEC standard DDR2 and DDR3
memories available. A built-in error checking and correction (ECC) ensures very low bit-error
rates for reliable high-frequency operation. ECC is implemented on MVME2502.
The memory controller supports the following:
 16 GB of memory
 Asynchronous clocking from platform clock, with programmable settings that meets all
the SDRAM timing parameters.
 Up to four physical banks; each bank can be independently addressed to 64 Mbit to 4 Gbit
memory devices (depending on the internal device configuration with x8/x16/x32 data
ports).
 Chipset interleaving and partial array self-refresh.
 Data mask signal and read-modify-write for sub-double-word writes when ECC is enabled.
 Double-bit error detection and single-bit error correction ECC, 8-bit check work across 64-
bit data.
 Automatic DRAM initialization sequence or software-controlled initialization sequence
and automatic DRAM data initialization.
 Write leveling for DDR3 memories and supports up to eight posted refreshes.
4.2.3 PCI Express Interface
The PCI Express interface is compatible with the PCI Express Base Specification Rev. 1.0a. The
PCI Express controller connects the internal platform to a 2.5 GHz serial interface. The P2020
has options for up to three PCIe interfaces with up to x4 link width. The PCIe controller is
configured to operate as either PCIe root complex (RC) or as an endpoint (EP) device.