Artesyn MVME2502 Installation and Use (April 2015) - Manual (Page 86)

Functional Description
MVME2502 Installation and Use (6806800R96E) 86
4.2.4 Local Bus Controller (LBC)
The main component of the enhanced LBC is the memory controller that provides a 16-bit
interface to various types of memory devices and peripherals. The memory controller is
responsible for controlling eight memory banks shared by the following: a general purpose
chip select machine (GPCM); a flash controller machine (FCM), and user programmable
machines (UPMs). The MVME2502 supports the GPCM, to interface with the CPLD, MRAM, and
QUART.
4.2.5 Secure Digital Host Controller (SDHC)
The ENP1 and ENP2 variants of the MVME2502 use a soldered down 8GB eMMC device
connected to the SDHC interface of the P2020 Processor. This is the only device available on
the SDHC interface.
4.2.6 I
2
C Interface
The MVME2502 has two independent I
2
C buses on the processor. The MVME2502 use port 2
for the XMC modules and the I2C port 1 for all other devices. For more information, see I2C
Devices, on page 101 .
4.2.7 USB Interface
The P2020 implements a USB 2.0 compliant serial interface engine. For more information, see
USB, on page 100 .
4.2.8 DUART
The chipset provides two universal asynchronous receiver/transmitter (UART). Each UART is
clocked by the CCB clock and is compatible with PC16522D. As a full-duplex interface, it
provides 16-byte FIFO for both transmitter and receiver mode.