Artesyn MVME2502 Installation and Use (April 2015) - Manual (Page 116)

Memory Maps and Registers
MVME2502 Installation and Use (6806800R96E) 116
5.5.5 PLD Sequence Register
The MVME2502 PLD provides an 8-bit register which contains the sequence of the PLD which
is in synchrony with the PCB version.
5.5.6 PLD Power Good Monitor Register
The MVME2502 PLD provides an 8-bit register which indicates the instantaneous status of the
supply’s power good signals.
Field PLD_REV
OPER R
RESET 0x05
Table 5-7 PLD Day Register
REG PLD Revision Register - 0xFFDF0006
Table 5-8 PLD Sequence Register
REG PLD Revision Register - 0xFFDF0007
Bit 7 6 5 4 3 2 1 0
Bit 7 6 5 4 3 2 1 0
Field PLD_REV
OPER R
RESET 0x00
Table 5-9 PLD Power Good Monitor Register
REG PLD PWRDG_MNTR - 0xFFDF0012
Bit 7 6 5 4 3 2 1 0
Field RSVD PWR_V
1P05_P
WRGD PWR_V
1P2_PW
RGD PWR_V
1P8_PW
RGD PWR_V
3P3_PW
RGD PWR_V
2P5_PW
RGD PWR_V
1P2_SW
_PWRG
D PWR_V
1P5_PW
RGD
OPER R