National CP3BT26 - Manual (Page 50)

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CP3BT26
10.4 MASKABLE INTERRUPT SOURCES
Table 20 shows the interrupts assigned to various on-chip
maskable interrupts. The priority of simultaneous maskable
interrupts is linear, with IRQ47 having the highest priority.
Table 20 Maskable Interrupts Assignment
All reserved interrupt vectors should point to default or error
interrupt handlers.
10.5 NESTED INTERRUPTS
Nested NMI interrupts are always enabled. Nested
maskable interrupts are disabled by default, however an in-
terrupt handler can allow nested maskable interrupts by set-
ting the I bit in the PSR. The LPR instruction is used to set
the I bit.
Nesting of specific maskable interrupts can be allowed by
disabling interrupts from sources for which nesting is not al-
lowed, before setting the I bit. Individual maskable interrupt
sources can be disabled using the IENAM0 and IENAM1
registers.
Any number of levels of nested interrupts are allowed, limit-
ed only by the available memory for the interrupt stack.
IRQ Number Description
IRQ47 TWM (Timer 0)
IRQ46 Bluetooth LLC 0
IRQ45 Bluetooth LLC 1
IRQ44 Bluetooth LLC 2
IRQ43 Bluetooth LLC 3
IRQ42 Bluetooth LLC 4
IRQ41 Bluetooth LLC 5
IRQ40 USB Interface
IRQ39 DMA Channel 0
IRQ38 DMA Channel 1
IRQ37 DMA Channel 2
IRQ36 DMA Channel 3
IRQ35 CAN
IRQ34 Advanced Audio Interface (AAI)
IRQ33 UART0 RX
IRQ32 CVSD/PCM Converter
IRQ31 ACCESS.bus
IRQ30 TA (Timer input A)
IRQ29 TB (Timer input B)
IRQ28 VTUA (VTU Interrupt Request 1)
IRQ27 VTUB (VTU Interrupt Request 2)
IRQ26 VTUC (VTU Interrupt Request 3)
IRQ25 VTUD (VTU Interrupt Request 4)
IRQ24 Microwire/SPI RX/TX
IRQ23 UART0 TX
IRQ22 UART0 CTS
IRQ21 Reserved
IRQ20 UART1 RX
IRQ19 UART1 TX
IRQ18 UART2 RX
IRQ17 UART2 TX
IRQ16 UART3 RX
IRQ15 UART3 TX
IRQ14 Reserved
IRQ13 ADC (Done)
IRQ12 MIWU Interrupt 0
IRQ11 MIWU Interrupt 1
IRQ10 MIWU Interrupt 2
IRQ9 MIWU Interrupt 3
IRQ8 MIWU Interrupt 4
IRQ7 MIWU Interrupt 5
IRQ6 MIWU Interrupt 6
IRQ5 MIWU Interrupt 7
IRQ4 Reserved
IRQ3 Random Number Generator (RNG)
IRQ2 Reserved
IRQ1 Flash Program/Data Memory
IRQ0 Reserved
IRQ Number Description