National CP3BT26 - Manual (Page 180)

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CP3BT26
MWDAT register is transmitted on MDIDO,
whether or not the data is valid.
0 – Echo back disabled.
1 – Echo back enabled.
EIO The Enable Interrupt on Overrun bit enables
or disables the overrun error interrupt. When
set, an interrupt is generated when the Re-
ceive Overrun Error bit (MWSTAT.OVR) is set.
Otherwise, no interrupt is generated when an
overrun error occurs. This bit must only be en-
abled in master mode.
0 – Disable overrun error interrupts.
1 – Enable overrun error interrupts.
EIR The Enable Interrupt for Read bit controls
whether an interrupt is generated when the
read buffer becomes full. When set, an inter-
rupt is generated when the Read Buffer Full
bit (MWSTAT.RBF) is set. Otherwise, no inter-
rupt is generated when the read buffer is full.
0 – No read buffer full interrupt.
1 – Interrupt when read buffer becomes full.
EIW The Enable Interrupt for Write bit controls
whether an interrupt is generated when the
Busy bit (MWSTAT.BSY) is cleared, which in-
dicates that a data transfer sequence has
been completed and the read buffer is ready
to receive the new data. Otherwise, no inter-
rupt is generated when the Busy bit is cleared.
0 – No interrupt on data transfer complete.
1 – Interrupt on data transfer complete.
SCM The Shift Clock Mode bit selects between the
normal clocking mode and the alternate clock-
ing mode. In the normal mode, the output data
is clocked out on the falling edge of MSK and
the input data is sampled on the rising edge of
MSK. In the alternate mode, the output data is
clocked out on the rising edge of MSK and the
input data is sampled on the falling edge of
MSK.
0 – Normal clocking mode.
1 – Alternate clocking mode.
SCIDL The Shift Clock Idle bit controls the value of
the MSK output when the Microwire module is
idle. This bit must be changed only when the
Microwire module is disabled (MEN = 0) or
when no bus transaction is in progress (MW-
STAT.BSY = 0).
0 – MSK is low when idle.
1 – MSK is high when idle
SCDV The Shift Clock Divider Value field specifies
the divisor used for generating the MSK shift
clock from the System Clock. The divisor is 2
× (SCDV[6:0] + 1). Valid values are 0000001b
to 1111111b, so the division ratio may range
from 3 to 256. This field is ignored in slave
mode (MWCTL1.MNS=0).
23.5.3 Microwire Status Register (MWSTAT)
The MWSTAT register is a word-wide, read-only register
that shows the current status of the Microwire interface
module. At reset, all non-reserved bits are clear. The regis-
ter format is shown below.
BSY The Busy bit, when set, indicates that the Mi-
crowire shifter is busy. In master mode, the
BSY bit is set when the MWDAT register is
written. In slave mode, the bit is set on the first
leading edge of MSK when MWCS is assert-
ed or when the MWDAT register is written,
whichever occurs first. In both master and
slave modes, this bit is cleared when the Mi-
crowire data transfer sequence is completed
and the read buffer is ready to receive the new
data; in other words, when the previous data
held in the read buffer has already been read.
If the previous data in the read buffer has not
been read and new data has been received
into the shift register, the BSY bit will not be
cleared, as the transfer could not be complet-
ed because the contents of the shift register
could not be transferred into the read buffer.
0 – Microwire shifter is not busy.
1 – Microwire shifter is busy.
RBF The Read Buffer Full bit, when set, indicates
that the Microwire read buffer is full and ready
to be read by software. It is set when the
shifter loads the read buffer, which occurs
upon completion of a transfer sequence if the
read buffer is empty. The RBF bit is updated
when the MWDAT register is read. At that
time, the RBF bit is cleared if the shifter does
not contain any new data (in other words, the
shifter is not receiving data or has not yet re-
ceived a full byte of data). The RBF bit re-
mains set if the shifter already holds new data
at the time that MWDAT is read. In that case,
MWDAT is immediately reloaded with the new
data and is ready to be read by software.
0 – Microwire read buffer is not full.
1 – Microwire read buffer is full.
OVR The Receive Overrun Error bit, when set in
master mode, indicates that a receive overrun
error has occurred. This error occurs when
the read buffer is full, the 8-bit shifter is full,
and a new data transfer sequence starts. This
bit is undefined in slave mode. The OVR bit,
once set, remains set until cleared by soft-
ware. Software clears this bit by writing a 1 to
its bit position. Writing a 0 to this bit position
has no effect. No other bits in the MWSTAT
register are affected by a write operation to
the register.
0 – No receive overrun error has occurred.
1 – Receive overrun error has occurred.
15 3 2 1 0
Reserved OVR RBF BSY